Semiconductor chip with seal ring and sacrificial corner pattern

1. A semiconductor device, comprising:

a low dielectric constant film having a relative dielectric constant less than 3.5;

a seal ring which is a moisture blocking wall forming a closed loop in a plan view; and

a sacrifice pattern group that includes a plurality of the sacrifice patterns,

wherein said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip,

wherein a passivation film covers said low dielectric constant film and the seal ring, and has a opening penetrating the passivation film, the opening formed in a vicinity of two chip end surfaces in a plan view, said two chip end surfaces forming the corner of the chip,

wherein a sacrifice pattern is provided outside of said sealing protrusion portion of the seal ring from a center of a chip,

wherein the sacrifice pattern is a structure in wall-form for preventing progress of a crack

wherein said passivation film is made of a SiN,

wherein said seal rings includes a Cu seal ring and Al seal ring formed above said Cu seal ring and said sacrifice pattern includes a Cu sacrifice pattern,

wherein an Al sacrifice pattern is not formed above said sacrifice pattern,

wherein said plurality of the sacrifice patterns has a linked layer of which the portions are connected to each other, and

wherein said linked layer is in mesh form in a plan view.