Semiconductor device with selectively etched surface passivation
View Patent ↗A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
1. A method of fabricating a semiconductor device, the method comprising:
defining an active area of the semiconductor device along a surface of a semiconductor substrate;
depositing an etch stop dielectric layer on the surface in the active area;
patterning the etch stop dielectric layer to expose a portion of the active area;
depositing a passivation layer on the etch stop dielectric layer and on the surface of the semiconductor substrate in the exposed portion of the active area; and
defining a gate area by dry etching the passivation layer.
2. The method of claim 1 , wherein:
defining the gate area comprises removing the etch stop dielectric layer in the gate area via a wet etch; and
the method further comprises forming a Schottky contact in the gate area.
3. The method of claim 1 , wherein the semiconductor substrate includes a base substrate and first and second Group III-nitride semiconductor layers epitaxially grown on the base substrate.
4. The method of claim 3 , wherein the passivation layer comprises low pressure chemical vapor deposition (LPCVD) silicon nitride.
5. The method of claim 1 , wherein the etch stop dielectric layer comprises aluminum oxide.
6. The method of claim 1 , wherein the etch stop dielectric layer comprises a material having an etch selectivity to block an etchant of the passivation layer from reaching the surface of the semiconductor substrate, the etchant being used in defining the gate area.
7. The method of claim 1 , wherein the exposed portion is disposed between the gate area and an area in which the passivation layer is deposited on the etch stop dielectric layer.
8. The method of claim 1 , wherein the gate area abuts an area in which the passivation layer is deposited on the etch stop dielectric layer.
9. The method of claim 1 , further comprising:
removing the passivation layer via a dry etch in respective areas for first and second ohmic contacts;
removing the etch stop dielectric layer in the respective areas for the first and second ohmic contacts via a wet etch; and
forming the first and second ohmic contacts in the respective areas.
10. The method of claim 9 , wherein patterning the etch stop dielectric layer is implemented before removing the passivation layer via the dry etch.
11. The method of claim 9 , wherein defining the gate area is implemented after forming the first and second ohmic contacts.
12. A method of fabricating a semiconductor device, the method comprising:
defining an active area of the semiconductor device along a surface of a semiconductor substrate;
depositing an etch stop dielectric layer on the surface in the active area;
patterning the etch stop dielectric layer to expose a portion of the active area;
depositing a passivation layer on the etch stop dielectric layer and on the surface of the semiconductor substrate in the exposed portion of the active area;
defining ohmic contact areas via a dry etch to remove the passivation layer and via a wet etch to remove the etch stop dielectric layer;
forming ohmic contacts in the ohmic contact areas; and
defining a gate area by dry etching the passivation layer.
13. The method of claim 12 , wherein:
defining the gate area comprises removing the etch stop dielectric layer in the gate area via a further wet etch; and
the method further comprises forming a Schottky contact in the gate area.
14. The method of claim 12 , further comprising forming a gate on the etch stop dielectric layer in the gate area.
15. The method of claim 14 , wherein the etch stop dielectric layer terminates beyond an overhang of the gate in the gate area.
16. The method of claim 12 , wherein:
the semiconductor substrate includes a base substrate and first and second Group III-nitride semiconductor layers epitaxially grown on the base substrate;
the passivation layer comprises low pressure chemical vapor deposition (LPCVD) silicon nitride; and
the etch stop dielectric layer comprises aluminum oxide.
17. The method of claim 12 , wherein the second dielectric layer comprises a material having an etch selectivity to block an etchant of the passivation layer from reaching the surface of the semiconductor substrate, the etchant being used in defining the ohmic contact areas and in defining the gate area.
18. The method of claim 12 , wherein the exposed portion is disposed between the gate area and an area in which the passivation layer is deposited on the etch stop dielectric layer.
19. The method of claim 12 , wherein the gate area abuts an area in which the passivation layer is deposited on the etch stop dielectric layer.
20. The method of claim 12 , wherein the etch stop dielectric layer does not abut the ohmic contacts.