IP Library Granted Patent US 9,082,505
Granted Patent B2
US 9,082,505 · App. 14/605,724 · Granted Jul 14, 2015

Method for triggering a delay-locked loop (DLL) update operation or an impedance calibration operation in a dynamic random access memory device

Inventor: Toru Ishikawa (Tokyo, JP)
Assignee: PS4 Luxco S.a.r.l.
G11C11/406
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Quick Facts
Patent No.
US 9,082,505
App. No.
14/605,724
Granted
Jul 14, 2015
Kind
B2
Abstract

A method for triggering an adjustment operation in a dynamic random access memory device, the method including receiving a refresh command, generating an execute signal, counting the execute signal to provide a count value, refreshing a memory array based on the count value and triggering the adjustment operation when the count value reaches a predetermined value.

Claims (16)

1. A method for triggering an adjustment operation in a dynamic random access memory device, the method comprising:

receiving a refresh command;

generating an execute signal;

counting the execute signal to provide a count value;

refreshing a memory array based on the count value; and

triggering the adjustment operation when the count value reaches a predetermined value.

2. The method as claimed in claim 1 , wherein the count value selects a word line in the memory array to be refreshed.

3. The method as claimed in claim 1 , wherein the memory array is not refreshed when the count value reaches the predetermined value.

4. The method as claimed in claim 1 , wherein the memory array is refreshed a plurality of times for each time the adjustment operation is triggered.

5. The method as claimed in claim 4 , wherein the plurality of times is 32 times.

6. The method as claimed in claim 1 , wherein the predetermined value is 0.

7. The method as claimed in claim 1 , wherein the adjustment operation is a DLL (Delay-Locked Loop) update operation.

8. The method as claimed in claim 1 , wherein the adjustment operation is a ZQ calibration operation.

9. The method as claimed in claim 1 , further comprising setting a mode register to enable the adjustment operation.

10. The method as claimed in claim 1 , further comprising setting a mode register to select the adjustment operation.

11. The method as claimed in claim 10 , wherein the mode register selects one or both of a DLL (Delay-Locked Loop) update operation and a ZQ calibration operation.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046865/0667 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
Priority Claims (1)
JP 2010-050018 · Mar 8, 2010 · national
Continuity (2)
Continuation 12929965 · Feb 28, 2011
Related Publication 20150131395A1 · May 14, 2015