Elastic gear first-in-first-out buffer with frequency monitor

1. An elastic gear First-in-First-out (FIFO) buffer, comprising:

an input that is configured to receive write data from a first device operating with a first local clock domain;

a plurality of memory cells that receive and temporarily store the write data received from the input;

an output that is configured to provide write data from the plurality of memory cells to a second device operating with a second local clock domain that is different from the first local clock domain;

a frequency monitor that controls and monitors a difference between the first local clock domain and the second local clock domain and, based on the difference, determines whether to instruct a pointer movement controller to adjust one or both of a write pointer and a read pointer for the plurality of memory cells, thereby allowing the elastic gear FIFO buffer to balance data flowing from the input to the output; and

an elastic reset module that initializes a virtual depth for the plurality of memory cells, wherein the elastic reset module comprises a read reset control and a write reset control, wherein the read reset control include a domain synchronization module and a delay module with a configurable delay.

2. The elastic gear FIFO buffer of claim 1 , wherein the frequency monitor comprises a write counter and a read counter, wherein the write counter counts starting from zero and increases by one every one write clock cycle in the first local clock domain, wherein the read counter counts starting at zero and increases by one every read clock cycle in the second local clock domain.

3. The elastic gear FIFO buffer of claim 2 , wherein the write counter counts to m−1, where m is a function of read clock frequency in the second local clock domain and a greatest common divider between the read clock frequency and write clock frequency in the first local clock domain.

4. The elastic gear FIFO buffer of claim 3 , wherein the read counter counts to n−1, where n is a function of the write clock frequency and the greatest common divider between the read clock frequency and the write clock frequency.

5. The elastic gear FIFO buffer of claim 4 , wherein m−1 corresponds to a write counter maximum value, wherein n−1 corresponds to a read counter maximum value, and wherein the write counter is mapped to at least one of Gray code and reduced Gray code before being transferred to the second local clock domain.

6. The elastic gear FIFO buffer of claim 5 , wherein the write counter, once transferred to the second local clock domain, is evaluated every time the read pointer reaches zero, and wherein evaluation of the write counter results in a calculation of a clock frequency drift to determine whether the write pointer or read pointer requires an adjustment.

7. The elastic gear FIFO buffer of claim 1 , wherein the elastic reset module is configured to implement a reset of at least one of the read pointer and write pointer and after the at least one of the read pointer and write pointer have been reset, the elastic reset module communicate the virtual depth to the frequency monitor for balancing the plurality of memory cells.

8. A system for transferring data from a first device operating with a first local clock domain to a second device operating with a second local clock domain, the system comprising:

a First-in-First-out (FIFO) buffer comprising a plurality of buffer memory cells;

a first input configured to receive information regarding a clock frequency in the first local clock domain;

a second input configured to receive information regarding a clock frequency in the second local clock domain;

a frequency monitor that transfers a clock frequency monitored result in the first local clock domain into the second local clock domain so that the clock frequency monitored result in the first local clock domain compares to the clock frequency in the second local clock domain and, based on the comparison, determines whether to instruct a pointer movement controller to adjust at least one of a read pointer and write pointer; and

an elastic reset that controls a FIFO initialize virtual depth, wherein the FIFO initialize virtual depth is configurable so that data latency through the FIFO initialize virtual depth is optimized on both a data width conversion between the first device and second device as well as a clock frequency tolerance design requirements, and wherein the frequency monitor is further configured to determine whether to instruct the pointer movement controller to adjust the at least one of a read pointer and write pointer based on the FIFO initialize virtual depth.

9. The system of claim 8 , wherein the frequency monitor comprises a write counter and a read counter, wherein the write counter counts starting from zero and increases by one every one write clock cycle in the first local clock domain, wherein the read counter counts starting at zero and increases by one every read clock cycle in the second local clock domain, wherein the write counter counts to m−1, where m is a function of read clock frequency in the second local clock domain and a greatest common divider between the read clock frequency and write clock frequency in the first local clock domain, wherein the read counter counts to n−1, where n is a function of the write clock frequency and the greatest common divider between the read clock frequency and the write clock frequency, wherein m−1 corresponds to a write counter maximum value, wherein n−1 corresponds to a read counter maximum value, and wherein the write counter is mapped to at least one of Gray code and reduced Gray code before being transferred to the second local clock domain.

10. The system of claim 9 , wherein the write counter, once transferred to the second local clock domain, is evaluated every time the read pointer reaches zero, and wherein evaluation of the write counter results in a calculation of a clock frequency drift to determine whether the write pointer or read pointer requires an adjustment.

11. A method of transferring data from a first device operating with a first local clock domain to a second device operating with a second local clock domain, the method comprising:

receiving data in a First-in-First-out (FIFO) buffer, wherein the received data is received from the first device;

temporarily storing the received data in the FIFO buffer;

reading the data stored from the FIFO buffer according to an order in which the data was received in the FIFO buffer, wherein the data is read to the second device;

monitoring a clock frequency in the first local clock domain;

monitoring a clock frequency in the second local clock domain;

transferring a clock frequency monitored result in the first local clock domain into the second local clock domain;

comparing the transferred clock frequency monitored result from the first local clock domain with the clock frequency in the second local clock domain;

based on the comparison, determining whether to instruct a pointer movement controller to increment at least one of a read pointer and write pointer to balance the FIFO buffer;

using an elastic reset to control a FIFO initialize virtual depth, wherein the FIFO initialize virtual depth is configurable so that data latency through the FIFO initialize virtual depth is optimized based on both a data width conversion between the first device and second device as well as clock frequency tolerance design requirements; and

determining, with the frequency monitor, whether or not to instruct the pointer movement controller to adjust the at least one of a read pointer and write pointer based on the FIFO initialize virtual depth.

12. The method of claim 11 , wherein the clock frequency in the first local clock domain is different from the clock frequency in the second local clock domain.

13. The method of claim 11 , wherein the pointer movement controller is provided with a gap move request instruction is response to determining that the clock frequency in the first local clock domain is drifting relative to the clock frequency in the second local clock domain.

14. The method of claim 11 , wherein the data received in the FIFO buffer is received at a different data width than the data is read out of the FIFO buffer.

15. The method of claim 11 , further comprising utilizing an elastic reset module to control a virtual depth of the FIFO buffer, wherein the determination of whether to instruct the pointer movement controller is also based on the virtual depth of the FIFO buffer.

16. An elastic gear First-in-First-out (FIFO) buffer, comprising:

an input that is configured to receive write data from a first device operating with a first local clock domain;

a plurality of memory cells that receive and temporarily store the write data received from the input;

an output that is configured to provide write data from the plurality of memory cells to a second device operating with a second local clock domain that is different from the first local clock domain; and

a frequency monitor that monitors a difference between the first local clock domain and the second local clock domain and, based on the difference, determines whether to instruct a pointer movement controller to adjust one or both of a write pointer and a read pointer for the plurality of memory cells, thereby allowing the elastic gear FIFO buffer to balance data flowing from the input to the output, wherein the frequency monitor comprises a write counter and a read counter, wherein the write counter counts starting from zero and increases by one every one write clock cycle in the first local clock domain, wherein the read counter counts starting at zero and increases by one every read clock cycle in the second local clock domain, and wherein the write counter counts to m−1, where m is a function of read clock frequency in the second local clock domain and a greatest common divider between the read clock frequency and write clock frequency in the first local clock domain.

17. The elastic gear FIFO buffer of claim 16 , wherein the read counter counts to n−1, where n is a function of the write clock frequency and the greatest common divider between the read clock frequency and the write clock frequency.

18. The elastic gear FIFO buffer of claim 17 , wherein m−1 corresponds to a write counter maximum value, wherein n−1 corresponds to a read counter maximum value.

19. The elastic gear FIFO buffer of claim 18 , wherein the write counter is mapped to at least one of Gray code and reduced Gray code before being transferred to the second local clock domain.

20. The elastic gear FIFO buffer of claim 19 , wherein the write counter, once transferred to the second local clock domain, is evaluated every time the read pointer reaches zero, and wherein evaluation of the write counter results in a calculation of a clock frequency drift to determine whether the write pointer or read pointer requires an adjustment.