Processor and method of controlling execution of processes
View Patent ↗A processor includes a plurality of processing sections, each of which executes a predetermined process. A plurality of fault detecting circuits are respectively provided for the plurality of processing sections, to detect a fault in one of the plurality of processing sections as a fault processing section to generate a fault detection signal. A fault monitoring and control section controls a normal processing section as at least one of the plurality of processing sections other than the fault processing section to execute a relieving process in response to the fault detection signal. The relieving process is determined based on a process load of the fault processing section, a process load of the normal processing section, and priority levels of processes to be executed by the fault processing section and the normal processing section.
1. A single chip processor comprising:
a first processing section;
a second processing section; and
a memory that is shared by the first and second processing sections, and that stores a first program for the first processing section and a second program for the second processing section,
wherein the first processing section is configured to execute the first program in a first predetermined time and the second processing section is configured to execute the second program in a second predetermined time, and
wherein when the fault occurs in the first processing section, the second processing section interrupts a running process for the second program and determines whether to execute either the first program or the second program.
2. The single chip processor according to claim 1 , wherein
the second processing section determines whether to execute either the first program or the second program based on priorities of the first and second programs.
3. The single chip processor according to claim 1 , wherein
the memory further stores a relieving program and the second processing section executes the relieving program to determine whether to execute either the first program or the second program.
4. The single chip processor according to claim 3 , wherein
the relieving program is configured to determine one of the first program and the second program based on priorities of the first and second programs.
5. The single chip processor according to claim 2 , wherein
when the priority of the first program is higher than the priority of the second program, the second processing section executes the first program.
6. The single chip processor according to claim 2 , wherein
when the priority of the first program is higher than the priority of the second program and the second processing section is able to execute the first and second programs in the second predetermined time, the second processing section executes the second program after execution of the first program.
7. The single chip processor according to claim 2 , wherein
when the priority of the second program is higher than the priority of the first program, the second processing section executes the second program.
8. The single chip processor according to claim 2 , wherein
when the priority of the second program is higher than the priority of the first program and the second processing section is able to execute the first and second programs in the second predetermined time, the second processing section executes the first program after execution of the second program.
9. The single chip processor according to claim 1 , further comprising:
a watchdog timer coupled to the first processing section, wherein the second processing section interrupts the running process for the second program and determines whether to execute either the first program or the second program when the watchdog timer indicates the fault in the first processing section.
10. The single chip processor according to claim 1 , wherein one of the first and second programs is a program to control an external device.
11. A single chip processor comprising:
a first processing section;
a second processing section;
a controller that controls the first and second processing sections if a fault occurs; and
a memory that is shared by the first and second processing sections, and that is configured to be accessed from the second processing section if the fault occurs in the first processing section,
wherein the memory stores a first program for the first processing section and a second program for the second processing section,
wherein the first processing section is configured to execute the first program in a first predetermined time and the second processing section is configured to execute the second program in a second predetermined time,
wherein the memory further stores a relieving program, the second processing section is interrupted and executes the relieving program when the fault occurs in the first processing section, and
wherein if the execution result of the relieving program indicates that a priority of the first program is higher than a priority of the second program, the second processing section executes the first program.
12. The single chip processor according to claim 11 , wherein
if the execution result of the relieving program further indicates that the second processing section is able to execute the first program and the second program in the second predetermined time, the second processing section executes the second program after execution of the first program.
13. The single chip processor according to claim 11 , further comprising:
a watchdog timer coupled to the first processing section, wherein the second processing section executes the relieving program when the watchdog timer indicates the fault in the first processing section.
14. The single chip processor according to claim 11 , wherein one of the first and second programs is a program to control an external device.
15. A single chip processor comprising:
a first processing section;
a second processing section;
a controller that controls the first and second processing sections if a fault occurs; and
a memory that is shared by the first and second processing sections, and that is configured to be accessed from the second processing section if the fault occurs in the first processing section,
wherein the memory stores a first program for the first processing section and a second program for the second processing section,
wherein the first processing section is configured to execute the first program in a first predetermined time and the second processing section is configured to execute the second program in a second predetermined time,
wherein the memory further stores a relieving program, the second processing section is interrupted and executes the relieving program when the fault occurs in the first processing section, and
wherein if the execution result of the relieving program indicates that a priority of the second program is higher than a priority of the first program, the second processing section executes the second program.
16. The single chip processor according to claim 15 , wherein
if the execution result of the relieving program further indicates that the second processing section is able to execute the first program and the second program in the second predetermined time, the second processing section executes the first program after execution of the second program.
17. The single chip processor according to claim 15 , further comprising:
a watchdog timer coupled to the first processing section, wherein the second processing section executes the relieving program when the watchdog timer indicates the fault in the first processing section.
18. The single chip processor according to claim 15 , wherein one of the first and second programs is a program to control an external device.