Method and apparatus for determining common node logical connectivity

1. A method for presenting synchronous cell connectivity in a semiconductor chip design, the method comprising:

receiving, at a microprocessor, a semiconductor chip design that comprises a plurality of objects therein, the objects including at least one of blocks, modules, macros, and cells;

bypassing, with the microprocessor, combinational logic of the objects in the semiconductor chip design to obtain a representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof; and

providing, with the microprocessor, a presentation of the semiconductor chip design based on the representation of the semiconductor chip design with the bypassed combinational logic of the objects.

2. The method of claim 1 , wherein registers, macros, and connections therebetween are included in the presentation of the semiconductor chip design and wherein the presentation of the semiconductor chip design excludes a presentation of the combinational logic.

3. The method of claim 1 , further comprising:

using the semiconductor chip design with the bypassed combinational logic to determine, with the microprocessor, connectivity weights for two or more objects of the semiconductor chip design, wherein connectivity weights are determined based on one or more of a number of connections between objects, a number of states of latency between objects, and timing distance between objects;

using the semiconductor chip design with the bypassed combinational logic to determine, with the microprocessor, connectivity for pins of the two or more objects;

based on the determined connectivity weights and connectivity for pins, determining, with the microprocessor, object groupings; and

presenting, with the microprocessor, the object groupings with the presentation of the semiconductor chip design.

4. The method of claim 3 , wherein each object grouping is colored differently in the presentation of the semiconductor chip design.

5. The method of claim 3 , further comprising:

using the object groupings to determine, with the microprocessor, a first automatic placement for the objects on the semiconductor chip design; and

creating, with the microprocessor, an adjusted semiconductor chip design that includes objects placed according to the determined first automatic placement for the objects.

6. The method of claim 5 , further comprising:

running, with the microprocessor, a legalization algorithm on the semiconductor chip design to ensure that each object is not overlapping any other object and further ensure that no object is placed beyond a semiconductor chip boundary.

7. The method of claim 3 , wherein timing distance is calculated by dividing a number of states of latency between a pair of objects by a clock period that occurs over the number of states of latency.

8. The method of claim 3 , further comprising:

determining, with the microprocessor, at least one sub-group within an object grouping; and

displaying, with the microprocessor, objects belonging to the at least one sub-group differently from other objects belonging to the object grouping but not the at least one sub-group.

9. The method of claim 1 , further comprising:

receiving, at the microprocessor, a presentation filter criteria that includes at least one type of object to be included or excluded from the presentation of the semiconductor chip design; and

applying the presentation filter criteria, with the microprocessor, so as to exclude or include objects in accordance with the presentation filter criteria.

10. The method of claim 1 , further comprising:

displaying, with the microprocessor one or more flylines that show at least one of node connectivity, common node connectivity, and extended timing path connectivity.

11. The method of claim 1 , further comprising:

based on the representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof, identifying, with the microprocessor, one or more common nodes that correspond to synchronous cells that are either being simultaneously driven by two other nodes or simultaneously driving two different nodes; and

highlighting, with the microprocessor, the one or more common nodes in the presentation of the semiconductor chip design.

12. The method of claim 1 , further comprising:

receiving, at the microprocessor, filter criteria for connectivity extraction; and

performing connectivity extraction, with the microprocessor, on less than every connection of the semiconductor chip design based on the filter criteria received for the connectivity extraction.

13. The method of claim 1 , wherein a cell represents a first-level abstraction of physical transistors and digital circuit components in the semiconductor chip, wherein a macro comprises one or multiple cells, wherein a module comprises one or multiple macros, and wherein a block comprises one or multiple modules.

14. A non-transitory computer-readable medium comprising processor-executable instructions that, when executed by a processor enable a presentation of synchronous cell connectivity in a semiconductor chip design, the instructions comprising:

instructions configured to receive a semiconductor chip design that comprises a plurality of objects therein, the objects including at least one of blocks, modules, macros, and cells;

instructions configured to bypass combinational logic of the objects in the semiconductor chip design to obtain a representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof; and

instructions configured to provide a presentation of the semiconductor chip design based on the representation of the semiconductor chip design with the bypassed combinational logic of the objects.

15. The computer-readable medium of claim 14 , wherein registers, macros, and connections therebetween are included in the presentation of the semiconductor chip design and wherein the presentation of the semiconductor chip design excludes a presentation of the combinational logic.

16. The computer-readable medium of claim 14 , further comprising:

instructions configured to use the semiconductor chip design with the bypassed combination logic to determine object groupings, wherein each object assigned to an object grouping is assigned thereto based on one or more of a number of connections between other objects in the object grouping, a number of states of latency between other objects in the object grouping, and timing distance between other objects in the object grouping; and

instructions configured to present the object groupings with the presentation of the semiconductor chip design.

17. The computer-readable medium of claim 15 , wherein each object grouping is colored differently in the presentation of the semiconductor chip design.

18. The computer-readable medium of claim 15 , further comprising:

instructions configured to use at least one of the object groupings and sub-groups to determine a first automatic placement for the objects on the semiconductor chip design; and

instructions configured to create an adjusted semiconductor chip design that includes objects placed according to the determined first automatic placement for the objects.

19. The computer-readable medium of claim 17 , further comprising:

instructions configured to run a legalization algorithm on the semiconductor chip design to ensure each object is not overlapping any other object and further ensure that no object is placed beyond a semiconductor chip boundary.

20. The computer-readable medium of claim 14 , further comprising:

instructions configured to receive a presentation filter criteria that includes at least one type of object to be included or excluded from the presentation of the semiconductor chip; and

instructions configured to apply the presentation filter criteria so as to exclude or include objects in accordance with the presentation filter criteria.

21. The computer-readable medium of claim 14 , further comprising:

instructions configured to, based on the representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof, identifying one or more common nodes that correspond to synchronous cells that are either being simultaneously driven by two other nodes or simultaneously driving two different nodes; and

instructions configured to highlight the one or more common nodes in the presentation of the semiconductor chip design.

22. A system that enables presentation of synchronous cell connectivity in a semiconductor chip design, the system comprising:

a microprocessor configured to execute computer-readable instructions; and

computer memory having instructions stored thereon that enable the microprocessor to:

receive a semiconductor chip design that comprises a plurality of objects therein, the objects including at least one of blocks, modules, macros, and cells;

bypass combinational logic of the objects in the semiconductor chip design to obtain a representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof; and

provide a presentation of the semiconductor chip design based on the representation of the semiconductor chip design with the bypassed combinational logic of the objects.

23. The system of claim 22 , wherein registers, macros, and connections therebetween are included in the presentation of the semiconductor chip design and wherein the presentation of the semiconductor chip design excludes a presentation of the combinational logic.