Semiconductor device
View Patent ↗A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n−x switch circuits to connect n−x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.
1. A semiconductor device comprising:
a plurality of n data circuits;
a plurality of n adjacent through silicon vias;
an auxiliary through silicon via;
a relief information circuit configured to provide a plurality of relief signals to identify a defective through silicon via x in the plurality of n through silicon vias, wherein x is an integer greater than 1 and n is an integer greater than x; and
a plurality of n switch circuits, the plurality of n switch circuits being configured so that x−1 switch circuits of the n switch circuits are activated based on the relief signals to connect x−1 data circuits to through silicon vias 1 to x−1 in the plurality of n adjacent through silicon vias, n−x switch circuits of the n switch circuits are activated based on the relief signals to connect n−x data circuits to through silicon vias x+1 to n in the plurality of n adjacent through silicon vias, and a switch circuit of the n switch circuits is activated based on the relief signals to connect a data circuit to the auxiliary through silicon via;
wherein each of the n switch circuits is configured to receive a data signal from a corresponding one of the n data circuits and to output the data signal to one of two through silicon vias of the n adjacent through silicon vias and the auxiliary through silicon via depending on the relief signals.
2. The semiconductor device as claimed in claim 1 , wherein the data circuit comprises a data driver circuit.
3. The semiconductor device as claimed in claim 1 , wherein the data circuit comprises a data receiver circuit.
4. The semiconductor device as claimed in claim 1 , wherein the plurality of relief signals provided by the relief information circuit comprises n relief signals.
5. The semiconductor device as claimed in claim 4 , wherein one of the n relief signals is activated when a corresponding through silicon via in the group of n adjacent through silicon vias is identified as defective.
6. The semiconductor device as claimed in claim 1 , further comprising an interface chip, wherein the plurality of relief signals is received from the interface chip.
7. The semiconductor device as claimed in claim 1 , wherein the plurality of relief signals is received from the relief information holding circuit.
8. The semiconductor device as claimed in claim 7 , wherein the relief information holding circuit comprises anti-fuse elements.
9. The semiconductor device as claimed in claim 7 , wherein the relief information holding circuit stores relief information supplied by a tester.
10. The semiconductor device as claimed in claim 9 , wherein the tester discovers the defective through silicon via by performing an operation test.
11. The semiconductor device as claimed in claim 1 , wherein the switch circuits comprise transfer gates.
12. The semiconductor device as claimed in claim 1 , wherein each of the n switch circuits comprise two transfer gates.
13. The semiconductor device as claimed in claim 1 , wherein the semiconductor device is one of a DRAM, SRAM, PRAM, MRAM, RRAM, flash memory, a CPU, or a DSP, or some combination thereof.