Semiconductor device with buffer and replica circuits

1. A semiconductor device, comprising:

an input buffer comprising:

first and second PMOS transistors serially interconnected between a first power supply node and an output node of the input buffer; and

first and second NMOS transistors serially interconnected between a second power supply node and the output node of the input buffer,

wherein a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to an input node of the input buffer, and a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor;

a replica circuit comprising:

third and fourth PMOS transistors serially interconnected between the first power supply node and an output node of the replica circuit; and

third and fourth NMOS transistors serially interconnected between the second power supply node and the output node of the replica circuit,

wherein a gate of the third PMOS transistor is connected to a gate of the third NMOS transistor, a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor are connected to an input node of the replica circuit, and the input node of the replica circuit is connected to the output node of the replica circuit; and

a comparison circuit that compares a voltage at the output node of the replica circuit to a reference voltage, an output voltage of the comparison circuit being connected to the gates of the second PMOS transistor and second NMOS transistor and to the gates of the third PMOS transistor and third NMOS transistor.

2. The semiconductor device as claimed in claim 1 , wherein the reference voltage is set between a voltage of the first power supply node and a voltage of the second power supply node.

3. The semiconductor device as claimed in claim 2 , wherein the reference voltage is adjustable by a programmable register.

4. The semiconductor device as claimed in claim 1 , wherein a plurality of replica circuits including the replica circuit is connected to the input buffer.

5. The semiconductor device as claimed in claim 1 , wherein a plurality of input buffers including the input buffer is connected to the replica circuit.

6. The semiconductor device as claimed in claim 1 , further comprising a voltage generating circuit for providing the reference voltage.

7. The semiconductor device as claimed in claim 6 , wherein the voltage generating circuit comprises a voltage dividing circuit.

8. The semiconductor device as claimed in claim 6 , wherein the voltage dividing circuit comprises a first and second resistors serially interconnected between the first power supply node and the second power supply node and providing the reference voltage at a node interconnecting the first and second resisters.

9. The semiconductor device as claimed in claim 1 , wherein the second PMOS transistor and the third PMOS transistor are directly connected to the first power supply and the second NMOS transistor and the third NMOS transistor are directly connected to the second power supply.

10. The semiconductor device as claimed in claim 1 , wherein the second power supply is a ground potential.

11. The semiconductor device as claimed in claim 1 , wherein the first power supply is VDD.

12. The semiconductor device as claimed in claim 1 , wherein the semiconductor device is a central processing unit.

13. The semiconductor device as claimed in claim 1 , wherein the semiconductor device is a dynamic random access memory.