System and method for dynamic Huffman decoding
A method of decoding a dynamic Huffman encoded data stream comprising receiving, by a processor, one or more input bits of encoded data from among an encoded data stream, searching, by the processor, a ternary content addressable memory (TCAM) for one or more codewords, accessing, by the processor, a plurality of random access memories (RAMs) that comprise the TCAM and have a maximum number of entries that is less than or equal to one half of two to a power of a maximum number of bits to be searched, reading a value from a first level RAM and using the value to index to a second level RAM, and outputting, by the processor, a codeword length and a decoded codeword value from either the first or second level RAM.
1. A method of decoding a dynamic Huffman encoded data stream comprising:
receiving, by a processor, one or more input bits of encoded data from among an encoded data stream;
searching, by the processor, a ternary content addressable memory (TCAM) for one or more codewords;
accessing, by the processor, a plurality of random access memories (RAMs) that comprise the TCAM and have a maximum number of entries that is less than or equal to one half of two to a power of a maximum number of bits to be searched;
reading, by the processor, a value from a first level RAM and using the value to index to a second level RAM; and
outputting, by the processor, a codeword length and a decoded codeword value from either the first or second level RAM.
2. The method of claim 1 , wherein the first level RAM is configured to decode up to N initial input bits of encoded data received and determine whether a match is found.
3. The method of claim 2 , further comprising outputting a codeword length and decoded codeword value from the first level of RAM in response to locating a matching codeword comprising N or fewer bits stored within the first level RAM.
4. The method of claim 2 , further comprising outputting an offset value and a value corresponding to a maximum additional number of bits required to address the second level RAM.
5. The method of claim 4 , further comprising adding the offset value to the value corresponding to the maximum additional number of bits and indexing the second level RAM for a matching codeword.
6. The method of claim 5 , further comprising outputting a codeword length and decoded codeword value from the second level RAM in response to locating a matching codeword stored within the second level RAM.
7. The method of claim 1 , further comprising loading code data in ascending order to the RAMs prior to the processor attempting to decode the input bits of the encoded data stream.
8. The method of claim 7 , further comprising loading to the first level RAM, a value indicating that a codeword length comprises N bits or less, a codeword length, and a codeword value comprising a number of clock cycles over which a load signal is active.
9. The method of claim 7 , further comprising:
loading to the first level RAM, a value indicating whether a codeword length either more than N bits or is less than or equal to N bits, a codeword offset, and a codeword value; and
loading to the second level of RAM at an address equal to a maximum additional number of bits of the codeword plus the codeword offset, the codeword length and the codeword value.
10. The method of claim 7 , further comprising writing to a plurality of RAM locations when a maximum codeword length is greater than the codeword length.
11. The method of claim 1 , wherein a plurality of TCAMs are searched and each TCAM is fed an offset position from the data stream.
12. The method of claim 11 , wherein any Huffman code present in the data stream at any offset is decoded and at least one correct Huffman code is subsequently selected.
13. The method of claim 12 , wherein N input bits is decoded per clock cycle.
14. A system for decoding a dynamic Huffman encoded data stream comprising:
a ternary content addressable memory (TCAM) comprising a plurality of random access memories (RAMs) having a maximum number of entries that is less than or equal to one half of two to a power of a maximum number of bits to be searched, the plurality of RAMs organized in levels comprising a first level RAM and a second level RAM; and
a processor configured to:
receive one or more input bits of encoded data from among an encoded data stream;
search the TCAM for one or more codewords by reading a value from the first level RAM and using the value to index to the second level RAM; and
output a codeword length and a decoded codeword value from either the first or second level RAM.
15. The system of claim 14 , wherein the first level RAM is configured to decode up to N initial input bits of encoded data received and determine whether a match is found.
16. The system of claim 15 , wherein the processor is further configured to output a codeword length and decoded codeword value from the first level of RAM in response to locating a matching codeword comprising N or fewer bits stored within the first level RAM.
17. The system of claim 15 , wherein the processor is further configured to output an offset value and a value corresponding to a maximum additional number of bits required to address the second level RAM.
18. The system of claim 17 , wherein the processor is further configured to add the offset value to the value corresponding to the maximum additional number of bits and indexing the second level RAM for a matching codeword.
19. The system of claim 18 , wherein the processor is further configured to output a codeword length and decoded codeword value from the second level RAM in response to locating a matching codeword stored within the second level RAM.
20. The system of claim 14 , wherein the processor is further configured to load code data in ascending order to the RAMs prior to the processor attempting to decode the input bits of the encoded data stream.
21. The system of claim 20 , wherein the processor is further configured to load to the first level RAM, a value indicating that a codeword length comprises N bits or less, a codeword length, and a codeword value comprising a number of clock cycles over which a load signal is active.
22. The system of claim 20 , wherein the processor is further configured to:
load to the first level RAM, a value indicating whether a codeword length either more than N bits or is less than or equal to N bits, a codeword offset, and a codeword value; and
load to the second level of RAM at an address equal to a maximum additional number of bits of the codeword plus the codeword offset, the codeword length and the codeword value.
23. The system of claim 20 , wherein the processor is further configured to write to a plurality of RAM locations when a maximum codeword length is greater than the codeword length.
24. The system of claim 14 , wherein the processor is further configured to search a plurality of TCAMs and feed each TCAM an offset position from the data stream.
25. The system of claim 24 , wherein any Huffman code present in the data stream at any offset is decoded and at least one correct Huffman code is subsequently selected.
26. The system of claim 25 , wherein N input bits is decoded per clock cycle.