IP Library Granted Patent US 9,236,302
Granted Patent B2
US 9,236,302 · App. 14/703,478 · Granted Jan 12, 2016

Semiconductor device and manufacturing method of semiconductor device

Inventors: Hikaru Ohira (Akishima, JP); Tamotsu Owada (Yokohama, JP); Hirosato Ochimizu (Kuwana, JP)
Assignee: FUJITSU SEMICONDUCTOR LIMITED
H01L21/76898H01L21/31055H01L21/31111H01L21/3212H01L21/7684H01L21/76877
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,236,302
App. No.
14/703,478
Granted
Jan 12, 2016
Kind
B2
Abstract

A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion.

Claims (29)

1. A manufacturing method of a semiconductor device comprising:

forming an electrically conductive layer extending from a first surface of a semiconductor substrate toward the side of a third surface up to part of the way;

forming a protrusion by forming a second surface by processing the semiconductor substrate from the side of the third surface to reduce the thickness of the semiconductor substrate and by protruding part of the electrically conductive layer from the second surface;

covering the protrusion by forming an insulation layer having a thickness greater than the length of the protrusion on the second surface; and

forming an opening in the insulation layer, through which to expose an end surface of the protrusion from the second surface, by reducing the thickness of the entire insulation layer and also processing the insulation layer and the protrusion so that the length of the protrusion becomes less than the thickness of the insulation layer, wherein

the processing the insulation layer and the protrusion comprises:

processing first the insulation layer so that the thickness of the entire insulation layer is reduced until the protrusion is exposed; and

processing second the protrusion so that the length of the protrusion becomes less than the thickness of the insulation layer.

2. The manufacturing method of a semiconductor device according to claim 1 , wherein

the processing the insulation layer and the protrusion processes the protrusion so that the end surface becomes concave toward the side of the first surface of the semiconductor substrate.

3. The manufacturing method of a semiconductor device according to claim 1 , wherein

the processing the insulation layer and the protrusion processes the protrusion so that the end surface becomes flat.

4. The manufacturing method of a semiconductor device according to claim 1 , wherein

the processing the insulation layer and the protrusion processes the insulation layer so that the periphery of the opening inclines toward the protrusion.

5. The manufacturing method of a semiconductor device according to claim 1 , wherein

the processing first has grinding.

6. The manufacturing method of a semiconductor device according to claim 5 , wherein

the polishing of the processing first uses slurry having any of abrasive grains including colloidal silica, an organic acid including a chelating agent, a citric acid, or an oxalic acid, an additive including ammonia water, potassium hydroxide, or a hydrogen peroxide solution, and a non-ionic detergent including polyethylene glycol.

7. The manufacturing method of a semiconductor device according to claim 1 , wherein

the processing second has a first processing rate for the insulation layer and a second processing rate for the electrically conductive layer, and

the second processing rate is higher than the first processing rate.

8. The manufacturing method of a semiconductor device according to 1 , wherein

the processing second has polishing or etching.

9. The manufacturing method of a semiconductor device according to claim 8 , wherein

the polishing of the processing second uses slurry comprising any of abrasive grains including colloidal silica, an organic acid including a citric acid, an oxalic acid, or a malic acid, an amino acid including glycine, and an additive including ammonia water, a hydrogen peroxide solution, a nitric acid, or benzotriazole.

10. The manufacturing method of a semiconductor device according to claim 8 , wherein

the etching of the processing second is wet etching using a hydrogen peroxide solution, a hydrofluoric acid, a nitric acid, a sulfuric acid, or a mixed solution thereof.

11. The manufacturing method of a semiconductor device according to claim 1 , wherein

before the processing the electrically conductive layer, an element layer is formed on the first surface of the semiconductor substrate.

Assignments (3)
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
Priority Claims (1)
JP 2013-085851 · Apr 16, 2013 · national
Continuity (2)
Division 14206545 · Mar 12, 2014
Related Publication 20150235901A1 · Aug 20, 2015