IP Library Granted Patent US 9,437,642
Granted Patent B2
US 9,437,642 · App. 14/716,125 · Granted Sep 6, 2016

Semiconductor device including a solid state imaging device

Inventor: Masatoshi Kimura (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
H01L27/14643H01L27/14603H01L27/14612H01L27/14641
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Quick Facts
Patent No.
US 9,437,642
App. No.
14/716,125
Granted
Sep 6, 2016
Kind
B2
Abstract

A semiconductor device is reduced in power consumption, the semiconductor device including a solid-state imaging device that includes pixels each having a plurality of light receiving elements. A pixel having first and second photodiodes is provided with a first transfer transistor that transfers charge in the first photodiode to a floating diffusion capacitance section, and a second transfer transistor that combines charge in the first photodiode and charge in the second photodiode, and transfers the combined charge to the floating diffusion capacitance section. Consequently, the semiconductor device is reduced in power required for activation of each transfer transistor in operation such as imaging with the solid-state imaging device.

Claims (27)

1. A semiconductor device, comprising:

a solid-state imaging device including a plurality of pixels, each of the plurality of pixels comprising:

a first light receiving element and a second light receiving element that each generate charge corresponding to light quantity of incident light,

a first transfer transistor that transfers charge in the first light receiving element to a floating diffusion capacitance section, and

a second transfer transistor that combines the charge in the first light receiving element and charge in the second light receiving element, and transfers the combined charge to the floating diffusion capacitance section.

2. The semiconductor device according to claim 1 ,

wherein the first transfer transistor has a source including the first light receiving element and a drain including the floating diffusion capacitance section, and

the second transfer transistor has a source including the first light receiving element and the second light receiving element and a drain including the floating diffusion capacitance section.

3. The semiconductor device according to claim 1 ,

wherein in imaging operation using the solid-state imaging device, the charge in the first light receiving element and the charge in the second light receiving element are combined and acquired as one pixel data.

4. The semiconductor device according to claim 3 ,

wherein in the imaging operation, the second transfer transistor is activated, thereby the charge in the first light receiving element and the charge in the second light receiving element are combined and read.

5. The semiconductor device according to claim 1 ,

wherein the pixel further includes

an amplifier transistor that outputs an electric signal corresponding to fluctuations in potential of the floating diffusion capacitance section,

a reset transistor that resets the potential of the floating diffusion capacitance section to a predetermined value, and

a selection transistor that externally outputs the electric signal output by the amplifier transistor,

wherein the reset transistor and the second transfer transistor are activated, thereby the charge in the first light receiving element and the charge in the second light receiving element are each initialized.

6. The semiconductor device according to claim 1 ,

wherein a first gate electrode as a component of the first transfer transistor is provided neighboring the first light receiving element, and

a second gate electrode as a component of the second transfer transistor is provided neighboring both the first light receiving element and the second light receiving element.

7. The semiconductor device according to claim 1 ,

wherein part of the second gate electrode as the component of the second transfer transistor is arranged between the first light receiving element and the second light receiving element in a plan view.

8. The semiconductor device according to claim 7 ,

wherein the first transfer transistor and the second transfer transistor are arranged in a first direction, and

the second gate electrode between the first light receiving element and the second light receiving element extends in a second direction perpendicular to the first direction.

9. The semiconductor device according to claim 1 , wherein the second transfer transistor separately receives the charge in the first light receiving element and the charge in the second light receiving element, combines the separately received charge in the first light receiving element and charge in the second light receiving element, and transfers the combined charge to the floating diffusion capacitance section.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044533/0739 →
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2015
From: KIMURA, MASATOSHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 035671/0434 →
Priority Claims (1)
JP 2014-116381 · Jun 5, 2014 · national
Continuity (1)
Related Publication 20150357365A1 · Dec 10, 2015