IP Library Granted Patent US 9,653,590
Granted Patent B2
US 9,653,590 · App. 14/747,060 · Granted May 16, 2017

Compound semiconductor device and method of manufacturing the same

Inventor: Junji Kotani (Atsugi, JP)
Assignee: FUJITSU LIMITED
H01L29/7787H01L21/0254H01L21/0262H01L21/02378H01L21/02381H01L21/02433H01L21/02458H01L29/167H01L29/66462H01L29/1075H01L29/2003
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Quick Facts
Patent No.
US 9,653,590
App. No.
14/747,060
Granted
May 16, 2017
Kind
B2
Abstract

A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon.

Claims (25)

1. A compound semiconductor device, comprising:

a semiconductor substrate;

a channel layer formed over the semiconductor substrate;

a carrier supply layer formed over the channel layer; and

a gate electrode, a source electrode and a drain electrode formed over the carrier supply layer,

the semiconductor substrate including an impurity-containing region containing impurities,

wherein the impurities are C or Mg, or combination thereof.

2. The compound semiconductor device as claimed in claim 1 , wherein a level of the impurities is lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the level of the impurities being higher than an upper edge of a valence band of silicon.

3. The compound semiconductor device as claimed in claim 1 , wherein the impurities are C.

4. The compound semiconductor device as claimed in claim 1 , wherein the impurities are Mg.

5. The compound semiconductor device as claimed in claim 1 , wherein the semiconductor substrate is a silicon substrate.

6. The compound semiconductor device as claimed in claim 1 , further comprising an initial layer containing AlN between the semiconductor substrate and the channel layer.

7. The compound semiconductor device as claimed in claim 6 , wherein the initial layer contains the impurities.

8. The compound semiconductor device as claimed in claim 6 , wherein the impurities exist at an interface between the semiconductor substrate and the initial layer.

9. The compound semiconductor device as claimed in claim 1 , further comprising a buffer layer containing AlGaN between the semiconductor substrate and the channel layer.

10. The compound semiconductor device as claimed in claim 9 , wherein the buffer layer is formed over an initial layer containing AlN, the initial layer formed between the semiconductor substrate and the channel layer.

11. The compound semiconductor device as claimed in claim 1 , further comprising a superlattice buffer layer in which first nitride semiconductor layers and second nitride semiconductor layers are repeatedly stacked.

12. The compound semiconductor device as claimed in claim 11 , wherein the superlattice buffer layer is formed over a buffer layer containing AlGaN, the buffer layer formed between the semiconductor substrate and the channel layer.

13. The compound semiconductor device as claimed in claim 11 , wherein the first semiconductor layer contains AlN.

14. The compound semiconductor device as claimed in claim 13 , wherein a thickness of the first semiconductor layer is 2 nm or less.

15. The compound semiconductor device as claimed in claim 11 , wherein the second semiconductor layer contains AlGaN.

16. The compound semiconductor device as claimed in claim 11 , wherein the first nitride semiconductor layers and the second nitride semiconductor layers are repeatedly stacked 80 periods in the superlattice buffer layer.

17. The compound semiconductor device as claimed in claim 1 , wherein a level of the impurities is higher than an upper edge of a valance band of silicon by 0.25 eV or more.

18. The compound semiconductor device as claimed in claim 1 , wherein an average impurity concentration is 1×10 18 cm −3 or more in a region from an upper surface to a depth of 50 nm of the semiconductor substrate.

19. The compound semiconductor device as claimed in claim 1 , wherein a carrier life time in the semiconductor substrate is 1×10 −9 seconds or less.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2015
From: KOTANI, JUNJI
To: FUJITSU LIMITED
Reel/Frame 036080/0208 →
Priority Claims (1)
JP 2014-129563 · Jun 24, 2014 · national
Continuity (1)
Related Publication 20150372125A1 · Dec 24, 2015