Semiconductor device with mechanical lock features between a semiconductor die and a substrate
View Patent ↗An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
1. A device comprising:
a semiconductor die having a bottom surface;
a substrate having a top surface;
a plurality of first mechanical lock features formed on the top surface of the substrate;
a plurality of second mechanical lock features formed on the bottom surface of the semiconductor die; and
a sintered metallic layer interspersed with the first and second mechanical lock features between the bottom surface of the semiconductor die and the top surface of the substrate.
2. The device of claim 1 , wherein the sintered metallic layer comprises a metallic material selected from sintered silver, sintered gold, sintered copper, sintered nickel, and sintered palladium.
3. The device of claim 1 , wherein the sintered metallic layer is formed from a die attach material that includes metallic particles configured to produce a sintered metal when exposed to a temperature sufficient for sintering to occur.
4. The device of claim 3 , wherein the metallic particles are selected from silver particles, gold particles, copper particles, nickel particles, and palladium particles.
5. The device of claim 3 , wherein the metallic particles have sizes in a range of 10 nanometers to 100 nanometers.
6. The device of claim 1 , wherein the first and second mechanical lock features are formed from a conductive material.
7. The device of claim 1 , wherein the first and second mechanical lock features are formed using a technique selected from selective chemical etching, sputter etching, and selective plating.
8. The device of claim 1 , wherein the sintered metallic layer includes an additive material configured to increase a thermal conductivity of the sintered metallic layer during operation of the device.
9. The device of claim 8 , wherein the additive material is selected from graphene, diamond particles, silicon carbide, titanium carbide, and boron nitride.
10. The device of claim 1 , wherein the substrate forms a portion of a structure that includes multiple interconnected substrates.
11. A device comprising:
a semiconductor die having a bottom surface with a conductive contact;
a substrate having a conductive top surface;
a plurality of first conductive mechanical lock features formed on the top surface of the substrate;
a plurality of second conductive mechanical lock features formed on the bottom surface of the semiconductor die; and
a sintered metallic layer interspersed with the first and second conductive mechanical lock features between the bottom surface of the semiconductor die and the top surface of the substrate.
12. The device of claim 11 , wherein the sintered metallic layer comprises a metallic material selected from sintered silver, sintered gold, sintered copper, sintered nickel, and sintered palladium.
13. The device of claim 11 , wherein the sintered metallic layer includes an additive material configured to increase a thermal conductivity of the sintered metallic layer during operation of the device.
14. The device of claim 13 , wherein the additive material is selected from graphene, diamond particles, silicon carbide, titanium carbide, and boron nitride.
15. The device of claim 11 , wherein the substrate is formed from a homogenous conductive material.
16. The device of claim 11 , wherein the substrate is formed from a bulk material with a conductive layer at the top surface of the substrate.
17. The device of claim 11 , wherein the semiconductor die is a field effect transistor, and the conductive contact is a conductive drain contact on the bottom surface of the semiconductor die.
18. The device of claim 11 , further comprising:
a plurality of leads;
an insulating structure that electrically insulates the plurality of leads from the top surface of the substrate; and
a plurality of wirebonds electrically coupled between the plurality of leads and the semiconductor die.
19. The device of claim 11 , further comprising:
a plurality of leads;
a plurality of wirebonds electrically coupled between the plurality of leads and the semiconductor die; and
encapsulation covering the die, the wirebonds, the top surface of the substrate, and portions of the plurality of leads.