Memory transistors with buried gate electrodes
View Patent ↗A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region arranged in that order in a first direction. A first side portion of the first active region and a second side portion of the second active region faces each other across a top surface of the channel region in the first direction. A gate electrode covers the top surface and the first and second side portions and extends in a second direction that intersects the first direction. A first diffusion layer is formed in the first active region. A second diffusion layer is formed in the second active region. An embedded contact plug is formed in the first active region and extends downwardly from the upper surface of the semiconductor region and contacts with the first diffusion layer.
1. A device comprising:
a first transistor having a first pillar-shaped semiconductor portion, a first vertical channel portion, a first horizontal channel portion and a first diffusion region, the first vertical channel portion and the first horizontal channel portion being arranged in a first direction and connected to each other to form an L-shaped channel, the first horizontal channel portion and the first diffusion region being arranged in the first direction and connected to each other, a first lower boundary of the first diffusion region being at a lower level than an first upper boundary of the first horizontal channel portion;
a first gate electrode covering a side portion of the first vertical channel portion and a top surface of first horizontal channel portion of the first transistor, the first gate electrode extending in a second direction that is substantially perpendicular to the first direction, the first gate electrode having a first top surface which is at a lower level than a top of the first pillar-shaped semiconductor portion; and
a contact plug being electrically connected to the first diffusion region, a lowest portion of the contact plug being at a lower level than the top surface of the first gate electrode, an upper portion of the contact plug being connected to a wiring layer, the wiring layer being at a level higher than a top surface of the first pillar-shaped semiconductor portion.
2. The device according to claim 1 , further comprising:
a second transistor having a second pillar-shaped semiconductor portion, a second vertical channel portion, a second horizontal channel portion and a second diffusion region, the second vertical channel portion and the second horizontal channel portion being arranged in the first direction and connected to each other to form an L-shaped channel, the second horizontal channel portion and the second diffusion region being arranged in the first direction and connected to each other, the first diffusion region of the first transistor and the second diffusion region of the second transistor being arranged in the first direction and electrically connected to each other, a second lower boundary of the second diffusion region being at a lower level than a second upper boundary of the second horizontal channel portions; and
a second gate electrode covering a side portion of the second vertical channel portion and a top surface of second horizontal channel portion, the second gate electrode extending in the second direction, the second gate electrode having a top surface which is at a lower level than a top of the second pillar-shaped semiconductor portion, wherein
the contact plug is electrically connected to the second diffusion region and intervenes between the first and the second diffusion regions, a lowest portion of the contact plug being at a lower level than the top surface of the second gate electrode.
3. The device according to claim 2 , wherein
the device is a memory device,
a data storage element is connected to an upper portion of the first pillar-shaped semiconductor portion, and
the first transistor and the second transistor are selection transistors.
4. The device according to claim 2 , wherein the contact plug at least contacts a sidewall of the first diffusion layer and a sidewall of the second diffusion layer.