Receiver architecture for a compact and low power receiver
View Patent ↗A circuit for a receiver with reconfigurable low-power or wideband operation may comprise one or more main signal paths each coupled to a first port and including a low-noise amplifier (LNA) configured to provide a radio frequency (RF) signal to a main mixer circuit. An auxiliary signal path may be coupled to a second port. The auxiliary signal path may include an auxiliary mixer configured to provide an on-chip matching input impedance that may match an impedance of the antenna. The first port may be coupled to an RF antenna through an off-chip matching circuit, when a low-power operation is desired. The first port may be coupled to the second port and to the RF antenna, when a wideband operation is desired.
1. A circuit for a compact and low power receiver, the circuit comprising:
a low-power low-noise amplifier (LNA) configured to amplify radio-frequency (RF) signals received from an RF antenna; and
a quadrature mixer coupled to a first and a second trans-impedance amplifiers (TIAs), wherein:
input and output nodes of the first and the second TIAs are cross-coupled via a first and a second resistor, and
the cross coupling is configured to create a complex impedance that replaces one or more LNA load inductors corresponding to one or more frequency bands of the receiver.
2. The circuit of claim 1 , wherein the input and out nodes of the first cross coupled TIA are coupled to output and input nodes of the second cross coupled TIA, via the first and the second resistors, respectively.
3. The circuit of claim 1 , wherein the created complex impedance is configured to replace the one or more LNA load inductors and to result in a substantial chip area reduction.
4. The circuit of claim 1 , wherein the low power LNA comprises a complementary inverter-based LNA with no degeneration inductors.
5. The circuit of claim 4 , wherein impedance matching is provided through one or more feedback capacitances including at least one of a parasitic capacitance or an additional on-chip feedback capacitance.
6. The circuit of claim 5 , wherein the additional on-chip feedback capacitance is implemented parallel to the parasitic capacitance, and wherein the parasitic capacitance comprises a parasitic gate-drain capacitances.
7. The circuit of claim 5 , wherein the low power LNA comprises a complementary inverter-based LNA, and wherein the parasitic capacitance comprises at least one of a parasitic gate-drain capacitance of NMOS or PMOS transistors of the complementary inverter-based LNA.
8. The circuit of claim 5 , wherein the impedance matching comprises tunable matching and is provided through one or more programmable feedback capacitances.
9. The circuit of claim 1 , wherein the LNA comprises a complementary inverter-based LNA, wherein the complementary inverter-based LNA is implemented on a substantially smaller area and is configured to consume approximately 50% less power, as compared to an inductor degenerated LNA.
10. A method for providing a compact and low power receiver, the method comprising:
providing a low-power low-noise amplifier (LNA);
configured the LNA to amplify radio-frequency (RF) signals received from an RF antenna;
coupling a quadrature mixer to a first and a second trans-impedance amplifiers (TIAs);
cross coupling input and output nodes of the first and the second TIAs via a first and a second resistor; and
configuring the cross coupling to create a complex impedance that replaces one or more LNA load inductors corresponding to one or more frequency bands of the compact and low power receiver.
11. The method of claim 10 , further comprising coupling the input and out nodes of the first cross coupled TIA to output and input nodes of the second cross coupled TIA, via the first and the second resistors, respectively.
12. The method of claim 10 , further comprising configuring the created complex impedance to substantially reduce chip area by replacing the one or more LNA load inductors.
13. The method of claim 10 , further comprising implementing the low power LNA using a complementary inverter-based LNA with no degeneration inductors.
14. The method of claim 13 , further comprising providing impedance matching through one or more feedback capacitances including at least one of a parasitic capacitance or an additional on-chip feedback capacitance.
15. The method of claim 14 , further comprising implementing the additional on-chip feedback capacitance parallel to the parasitic capacitance, and wherein the parasitic capacitance comprises a parasitic gate-drain capacitances.
16. The method of claim 15 , further comprising implementing the low power LNA using a complementary inverter-based LNA, and wherein the parasitic capacitance comprises at least one of a parasitic gate-drain capacitance of NMOS or PMOS transistors of the complementary inverter-based LNA.
17. The method of claim 10 , further comprising providing impedance matching through a tunable matching provided through one or more programmable feedback capacitances.
18. The method of claim 10 , further comprising:
implementing the low power LNA using a complementary inverter-based LNA; and
implementing the complementary inverter-based LNA on a substantially smaller area,
wherein the complementary inverter-based LNA is configured to consume approximately 50% less power, as compared to an inductor degenerated LNA.
19. A communication device comprising:
an radio-frequency (RF) antenna; and
a compact and low power receiver coupled to the RF antenna, the receiver comprising:
a low-power low-noise amplifier (LNA) configured to amplify RF signals received from the RF antenna; and
a quadrature mixer coupled to a first and a second trans-impedance amplifiers (TIAs),
wherein:
input and output nodes of the first and the second TIAs are cross-coupled via a first and a second resistor, and
the cross coupling is configured to create a complex impedance that replaces one or more LNA load inductors corresponding to one or more frequency bands of the receiver.
20. The communication device of claim 19 , wherein:
the input and out nodes of the first cross coupled TIA are coupled to output and input nodes of the second cross coupled TIA, via the first and the second resistors, respectively, and
the low power LNA comprises a complementary inverter-based LNA with no degeneration inductors.