Auxiliary self-protecting transistor structure
View Patent ↗This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.
1. An auxiliary self-protecting transistor circuit, comprising:
an electrostatic discharge (ESD) device including a gate terminal, a drain terminal, and a source terminal, wherein the drain terminal of the ESD device is configured to be coupled to an isolation well of a complementary metal-oxide semiconductor (CMOS) transistor,
wherein the ESD device is configured to provide a discharge path between the isolation well and the source terminal of the ESD device to protect the CMOS transistor.
2. The circuit of claim 1 , including a trigger circuit configured to provide a stimulus to the gate terminal of the ESD device to initiate conduction between the drain terminal and the source terminal of the ESD device.
3. The circuit of claim 2 , wherein the trigger circuit includes a capacitor coupled between a voltage rail and the gate terminal of the ESD device, and a resistor coupled between the gate terminal of the ESD device and ground.
4. The circuit of claim 1 , wherein the ESD device includes an n-type metal-oxide semiconductor (NMOS) transistor, and
wherein the drain terminal of the NMOS transistor is configured to receive a surge event from the isolation well and to discharge the surge event through the source terminal of the NMOS transistor to ground.
5. The circuit of claim 1 , wherein the isolation well includes at least one of an n-doped isolation well (niso) or a p-type well (pwell).
6. The circuit of claim 1 , wherein the CMOS transistor includes a gate terminal, a drain terminal, and a source terminal, and
wherein the drain terminal of the ESD device is not coupled to the gate terminal, the drain terminal, or the source terminal of the CMOS transistor.
7. The circuit of claim 1 , including a pass gate, wherein the pass gate includes the CMOS transistor, and
wherein the ESD device is configured to provide a discharge path to protect the pass gate from a surge event.
8. An auxiliary self-protecting transistor electrostatic discharge (ESD) system, comprising:
an ESD device including a gate terminal, a drain terminal, and a source terminal; and
a complementary metal-oxide semiconductor (CMOS) transistor including a gate terminal, a drain terminal, a source terminal, and an isolation well,
wherein the drain terminal of the ESD device is coupled to the isolation well,
wherein the ESD device is configured to provide a discharge path between the isolation well and the source terminal of the ESD device to protect the CMOS transistor.
9. The system of claim 8 , wherein the drain terminal of the ESD device is not coupled to the gate terminal, the drain terminal, or the source terminal of the CMOS transistor.
10. The system of claim 8 , including a trigger circuit configured to provide a stimulus to the gate terminal of the ESD device to initiate conduction between the drain terminal and the source terminal of the ESD device.
11. The system of claim 10 , wherein the trigger circuit includes a capacitor coupled between a voltage rail and the gate terminal of the ESD device, and a resistor coupled between the gate terminal of the ESD device and ground.
12. The system of claim 8 , wherein the ESD device includes an n-type metal oxide semiconductor (NMOS) transistor, and
wherein the drain terminal of the NMOS transistor is configured to receive a surge event from the isolation well and to discharge the surge event through the source terminal of the NMOS transistor to ground.
13. The system of claim 8 , wherein the isolation well includes at least one of an n-doped isolating isolation well (niso) or a p-type well (pwell).
14. The system of claim 8 , including a pass gate, wherein the pass gate includes the CMOS transistor, and
wherein the ESD device is configured to provide a discharge path to protect the pass gate from a surge event.
15. A method to provide auxiliary protection to a transistor, comprising:
coupling an isolation well of a complementary metal-oxide semiconductor (CMOS) transistor to a drain terminal of an electrostatic discharge (ESD) device; and
providing a discharge path between the isolation well and a source terminal of the ESD device to protect the CMOS transistor from a surge event.
16. The method of claim 15 , including providing a stimulus to a gate terminal of the ESD device using a trigger circuit to initiate conduction between the drain terminal and a source terminal of the ESD device.
17. The method of claim 16 , wherein the trigger circuit includes a capacitor coupled between a voltage rail and the gate terminal of the ESD device, and a resistor coupled between the gate terminal of the ESD device and ground.
18. The method of claim 15 , including:
receiving a surge event from the isolation well at the drain terminal of the ESD device; and
discharging the surge event through a source terminal of the ESD device to ground,
wherein the ESD device includes an n-type metal-oxide semiconductor (NMOS) transistor.
19. The method of claim 15 , wherein the isolation well includes at least one of an n-doped isolation well (niso) or a p-type well (pwell).
20. The method of claim 15 , wherein the CMOS transistor includes a gate terminal, a drain terminal, and a source terminal, and
wherein the drain terminal of the ESD device is not coupled to the gate terminal, the drain terminal, or the source terminal of the CMOS transistor.