Data bus efficiency via cache line usurpation
View Patent ↗Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
1. A system, comprising:
a cache;
a storage device; and
a memory controller coupled to the cache and operable to determine whether a piece of data is required for a system operation,
if the piece of data is not required for the system operation, the memory controller being operable to write the piece of data directly to the storage device while the cache is allocated for the piece of data, wherein the piece of data is not written to the cache during the write of the piece of data to the storage device,
if the piece of data is required for a system operation, the memory controller being operable to write the piece of data into the cache.
2. The system of claim 1 , the memory controller initializing a location in the cache through hardware, if the piece of data is not required for the system operation.
3. The system of claim 1 , the memory controller initializing a location in the cache if a location in the storage device is already associated with the cache.
4. The system of claim 1 , wherein the memory controller is operable to specify a number of cache lines to allocate.
5. The system of claim 1 , wherein the memory controller is operable to allocate a plurality of cache lines with a single request.
6. The system of claim 1 , wherein the memory controller is operable to initialize the cache according to a pattern.
7. A method of cache allocation, the method comprising:
determining whether a piece of data is required for a system operation,
writing, if the piece of data is not required for the system operation, the piece of data directly to a storage device while a cache location is allocated for the piece of data, wherein the piece of data is not written to the cache during the writing of the piece of data to the storage device, and
writing the piece of data to into the cache location, if the piece of data is required for the system operation.
8. The method of claim 7 , the method comprising initializing the cache location through hardware, if the piece of data is not required for the system operation.
9. The method of claim 7 , the method comprising initializing the cache location if a location in the storage device is already associated with the cache.
10. The method of claim 7 , the method comprising allocating a plurality of cache lines with a single request, if the piece of data is not required for the system operation.
11. The method of claim 7 , the method comprising allocating a plurality of cache lines with a single request.
12. The method of claim 7 , the method comprising initializing the cache location according to a pattern.
13. The method of claim 7 , the method comprising initializing the cache location to zero.
14. A network device with cache allocation, the network device comprising:
a cache;
a storage device; and
a hardware processor operable to write, if the piece of data is not required for a system operation, a piece of data directly to a storage device while the cache is allocated for the piece of data, wherein the piece of data is not written to the cache during the write of the piece of data to the storage device,
the hardware processor being operable to write the piece of data into the cache, if the piece of data is required for the system operation.
15. The network device of claim 14 , wherein the hardware processor is operable to initialize the cache if the piece of data is not required for the system operation.
16. The network device of claim 14 , wherein the hardware processor is operable to initialize the cache if the piece of data is not required for the system operation and a location in the storage device is already associated with the cache.
17. The network device of claim 14 , wherein the hardware processor is operable to allocate a plurality of cache lines with a single request, if the piece of data is not required for the system operation.
18. The network device of claim 14 , wherein the hardware processor is operable to allocate a plurality of cache lines with a single request.
19. The network device of claim 14 , wherein the hardware processor is operable to initialize the cache according to a pattern.
20. The network device of claim 14 , wherein the hardware processor is operable to initialize the cache to zero.