Semiconductor device verifying signal supplied from outside
Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
1. A method for controlling a memory device comprising:
supplying a chip select signal to the memory device;
supplying an address signal having a plurality of bits to the memory device;
supplying a command signal having a plurality of bits to the memory device;
generating a verification signal based on a selected one of the plurality of bits in the address signal and the plurality of bits in the command signal;
supplying the verification signal to the memory device; and
receiving an alert signal from the memory device indicating whether the memory device received the selected one of the plurality of bits in the address signal and the plurality of bits in the control signal with an error.
2. The method as claimed in claim 1 , wherein the chip select signal is supplied to the memory device before the address signal, the command signal, and the verification signal.
3. The method as claimed in claim 1 , wherein the address signal, the command signal, and the verification signal are supplied to the memory device at the same time.
4. The method as claimed in claim 1 , wherein the verification signal is based on both the plurality of bits in the address signal and the plurality of bits in the command signal.
5. The method as claimed in claim 1 , wherein the verification signal is a parity signal.
6. The method as claimed in claim 5 , wherein the verification signal has a low level if the selected one of the plurality of bits in the address signal and the plurality of bits in the control signal have an even number of high level bits.
7. The method as claimed in claim 5 , further comprising supplying a mode register setting command to the memory device to enable parity check.
8. The method as claimed in claim 1 , wherein the alert signal has a high level if the memory device received the selected one of the plurality of bits in the address signal and the plurality of bits in the command signal with an error.
9. The method as claimed in claim 1 , wherein the memory device is a DDR DRAM.
10. A system comprising:
a controller; and
a memory device;
wherein the controller generates a verification signal based on a selected one of a plurality of bits in an address signal and a plurality of bits in a control signal and the controller supplies a chip select signal, the command signal, the address signal, and the verification signal to the memory device; and
wherein the memory device generates an alert signal based on the verification signal and the selected one of the plurality of bits in the address signal and the plurality of bits in the control signal and the memory device supplies the alert signal to the controller.
11. The method as claimed in claim 9 wherein the controller supplies the chip select signal to the memory device before the address signal, the command signal, and the verification signal.
12. The method as claimed in claim 9 wherein the controller supplies the address signal, the command signal, and the verification signal to the memory device at the same time.
13. The method as claimed in claim 10 , wherein the verification signal is based on both the plurality of bits in the address signal and the plurality of bits in the control signal.
14. The method as claimed in claim 10 , wherein the verification signal is a parity signal.
15. The method as claimed in claim 14 , wherein the verification signal has a low level if the selected one of the plurality of bits in the address signal and the plurality of bits in the control signal have an even number of high level bits.
16. The method as claimed in claim 14 , wherein the controller supplies a mode register setting command to the memory device to enable parity check.
17. The method as claimed in claim 10 , wherein the alert signal has a high level if the memory device received the selected one of the plurality of bits in the address signal and the plurality of bits in the control signal with an error.
18. The method as claimed in claim 10 , wherein the memory device is a DDR DRAM.