IP Library Granted Patent US 9,438,241
Granted Patent B1
US 9,438,241 · App. 14/841,280 · Granted Sep 6, 2016

Multipurpose pads used as digital serial and analog interface

Inventors: Milos Davidovic (Vienna, AT); Kurt Schweiger (Vienna, AT); Robert Swoboda (Vienna, AT)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
H03K19/018571
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Quick Facts
Patent No.
US 9,438,241
App. No.
14/841,280
Granted
Sep 6, 2016
Kind
B1
Abstract

An Integrated Circuit, a system, and a method are provided. The disclosed Integrated Circuit may include a plurality of pads exposing internal components of the Integrated Circuit to external circuits, a digital interface connectable to the plurality of pads, an analog interface connectable to the plurality of pads, and sensing circuitry configured to detect whether a digital circuit or an analog circuit is externally connected to the plurality of pads and based on such detection selectively connect at least one of the digital interface and analog interface to the plurality of pads.

Claims (32)

1. An Integrated Circuit, comprising:

a plurality of pads exposing internal components of the Integrated Circuit to external circuits;

a digital interface connectable to the plurality of pads;

an analog interface connectable to the plurality of pads; and

sensing circuitry configured to detect whether a digital circuit or an analog circuit is externally connected to the plurality of pads and based on such detection selectively connect at least one of the digital interface and analog interface to the plurality of pads.

2. The Integrated Circuit of claim 1 , wherein only one of the digital interface and analog interface is capable of being connected to the plurality of pads at any given time.

3. The Integrated Circuit of claim 2 , wherein the sensing circuitry comprises impedance sensing circuitry.

4. The Integrated Circuit of claim 3 , wherein the impedance sensing circuitry detects whether an external circuit connected to the plurality of pads comprises an impedance within a specified range and in the event that the detected impedance is not within the specified range, then the analog interface is connected to the plurality of pads and the digital interface is disconnected from the plurality of pads.

5. The Integrated Circuit of claim 4 , wherein the specified range corresponds to an impedance range specified for Complementary Metal-Oxide-Semiconductor (CMOS) drivers of the internal components of the Integrated Circuit.

6. The Integrated Circuit of claim 3 , wherein the impedance sensing circuitry comprises an output buffer.

7. The Integrated Circuit of claim 1 , wherein the plurality of pads include a first input pad, a second input pad, and a third input pad.

8. The Integrated Circuit of claim 6 , wherein the plurality of pads include a fourth pad, wherein the fourth pad is capable of operating as an input pad or an output pad.

9. The Integrated Circuit of claim 1 , wherein the digital interface comprises a digital serial interface.

10. The Integrated Circuit of claim 1 , wherein the digital interface and analog interface are selectively connected to the plurality of pads by at least one of physical switches and logic signals provided to the digital interface and analog interface causing the digital interface and analog interface to turn ON and OFF.

11. A system, comprising:

an Integrated Circuit having a plurality of pads and an interface that connects the plurality of pads to internal components of the Integrated Circuit;

external circuitry connectable to the plurality of pads; and

a sensing module configured to detect whether the external circuitry corresponds to digital or analog circuitry and based on such detection switch the interface of the Integrated Circuit between an analog mode of operation and a digital mode of operation.

12. The system of claim 11 , wherein the sensing module comprises sensing circuitry incorporated in the Integrated Circuit.

13. The system of claim 11 , wherein the sensing module senses an impedance of the external circuitry to determine whether to operate the interface in the analog mode of operation or the digital mode of operation.

14. The system of claim 13 , wherein the sensing module causes the interface to operate in the digital mode of operation when the impedance of the external circuitry is determined to be less than a predetermined threshold.

15. The system of claim 13 , wherein the sensing module causes the interface to operate in the analog mode of operation when the impedance of the external circuitry is determined to be greater than or equal to a predetermined threshold.

16. The system of claim 11 , wherein the interface comprises both an analog interface and a digital interface, wherein while the interface is operating in the analog mode of operation the analog interface is connected to the plurality of pads and the digital interface is disconnected from the plurality of pads, and wherein while the interface is operating in the digital mode of operation the analog interface is disconnected from the plurality of pads and the digital interface is connected to the plurality of pads.

17. The system of claim 16 , wherein the digital interface comprises a digital serial interface, wherein the plurality of pads are used as digital serial interface pads during the digital mode of operation, and wherein the plurality of pads are used as analog current inputs and outputs during the analog mode of operation.

18. A method, comprising:

connecting external circuitry to an Integrated Circuit via a plurality of pads;

detecting, within the Integrated Circuit, whether the external circuitry corresponds to digital or analog circuitry; and

based on whether the external circuitry is detected as corresponding to digital or analog circuitry, switching an interface of the Integrated Circuit into one of a digital mode of operation and an analog mode of operation.

19. The method of claim 18 , wherein detecting whether the external circuitry corresponds to digital or analog circuitry comprises sensing an impedance of the external circuitry and wherein detecting whether the external circuitry corresponds to digital or analog circuitry further comprises comparing the sensed impedance of the external circuitry to an impedance threshold.

20. The method of claim 18 , further comprising:

determining whether each of the plurality of pads are connected to a same type of external circuitry; and

in the event that the plurality of pads are determined not to be connected to the same type of external circuitry, setting operational values of the Integrated Circuit to default operational values.

Assignments (7)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2015
From: DAVIDOVIC, MILOS; SCHWEIGER, KURT; SWOBODA, ROBERT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036609/0390 →