I/O COMMAND ID COLLISION AVOIDANCE IN A MEMORY DEVICE
Embodiments herein provide for avoiding ID collisions in a memory device. In one embodiment, a memory device includes slave logic operable to receive I/O commands from a plurality of master components and a memory controller operable to process the I/O commands from the master components to operate on data in the memory. Each I/O command comprises an ID assigned by its originating master component. The slave logic is further operable to determine the ID of a first I/O command from a first of the master components, to receive a second I/O command from a second of the master components having a same ID as the first I/O command while the first I/O command is being processed by the memory controller, and to stall the second I/O command until the first I/O command is complete while allowing other I/O commands with other IDs to access the memory.
1 . A memory device, comprising:
a memory;
slave logic operable to receive Input/Output (I/O) commands from a plurality of master components; and
a memory controller communicatively coupled to the slave interface and operable to process the I/O commands from the master components to operate on data in the memory,
wherein each I/O command comprises an identification (ID) assigned by its originating master component, and
wherein the slave logic is further operable to determine the ID of a first of the I/O commands from a first of the master components, to receive a second of the I/O commands from a second of the master components having a same ID as the first I/O command while the first I/O command is being processed by the memory controller, and to stall the second I/O command until the first I/O command is complete while allowing other I/O commands with other IDs to access the memory.
2 . The memory device of claim 1 , wherein:
the I/O commands are Advanced eXtensible Interface (AXI) I/O commands.
3 . The memory device of claim 1 , wherein:
the first and second I/O commands are read-modify-write commands.
4 . The memory device of claim 1 , further comprising:
an ID buffer operable to retain the ID of the first I/O command for a same number of clock cycles as used to complete the first I/O command.
5 . The memory device of claim 1 , further comprising:
a memory controller operable to process the first I/O command to a first location in the memory, to determine that the second I/O command is directed to the first memory location while the first I/O command is accessing the first memory location, and to stall the second I/O command until the first I/O command is complete while allowing a third I/O command to access the memory.
6 . The memory device of claim 5 , wherein:
the memory controller is further operable to extract an address of the memory location from the first I/O command, and to track the memory address until the first I/O command is complete.
7 . The method of claim 5 , wherein:
the command scheduler further comprises a state machine that is operable to extract a memory address of the second I/O command while the first I/O command is processing, and to compare the memory address of the second I/O command to the memory address extracted from the first I/O command.
8 . A method operable in a memory device, comprising:
determining an identification (ID) of a first I/O command from a first master component;
processing the first I/O command to operate on data in the memory device;
receiving a second I/O command from a second master component having a same ID as the first I/O command while the first I/O command is operating on the data; and
until the first I/O command is complete, stalling the second I/O command while
allowing a third I/O command with a different ID to access the memory device,
wherein each ID of each I/O command is assigned by its originating master component.
9 . The method of claim 8 , wherein:
the I/O commands are Advanced eXtensible Interface (AXI) I/O commands.
10 . The method of claim 8 , wherein:
the first and second I/O commands are read-modify-write commands.
11 . The method of claim 8 , further comprising:
retaining the ID of the first I/O command for a same number of clock cycles as used to complete the first I/O command.
12 . The method of claim 8 , further comprising:
processing the first I/O command to a first location in the memory;
determining that the second I/O command is directed to the first memory location while the first I/O command is accessing the first memory location; and
stalling the second I/O command until the first I/O command is complete while allowing the third I/O command to access the memory.
13 . The method of claim 12 , further comprising:
extracting an address of the memory location from the first I/O command; and
tracking the memory address until the first I/O command is complete.
14 . The method of claim 12 , further comprising:
extracting a memory address of the second I/O command while the first I/O command is processing; and
comparing the memory address of the second I/O command to the memory address extracted from the first I/O command.
15 . A non-transitory computer readable medium operable in a memory device that, when executed by logic in the memory device, directs the logic to:
determine an identification (ID) of a first I/O command from a first master component;
process the first I/O command to operate on data in the memory device;
receive a second I/O command from a second master component having a same ID as the first I/O command while the first I/O command is operating on the data; and
until the first I/O command is complete, stall the second I/O command while
allow a third I/O command with a different ID to access the memory device,
wherein each ID of each I/O command is assigned by its originating master component.
16 . The computer readable medium of claim 15 , wherein:
the first and second I/O commands are read-modify-write commands.
17 . The computer readable medium of claim 15 , further comprising instructions that direct logic to:
retain the ID of the first I/O command for a same number of clock cycles as used to complete the first I/O command.
18 . The computer readable medium of claim 15 , further comprising instructions that direct logic to:
process the first I/O command to a first location in the memory;
determine that the second I/O command is directed to the first memory location while the first I/O command is accessing the first memory location; and
stall the second I/O command until the first I/O command is complete while allowing the third I/O command to access the memory.
19 . The computer readable medium of claim 18 , further comprising instructions that direct logic to:
extract an address of the memory location from the first I/O command; and
track the memory address until the first I/O command is complete.
20 . The computer readable medium of claim 18 , further comprising instructions that direct logic to:
extract a memory address of the second I/O command while the first I/O command is processing; and
compare the memory address of the second I/O command to the memory address extracted from the first I/O command.