METHODS FOR DESIGNING PHOTONIC DEVICES
A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.
1 . A method of designing a photonic device, the method comprising:
identifying fabrication design rules of a fabrication process;
generating an initial device design by determining, with use of constraints of the fabrication design rules, a plurality of I/O ports and segments along a direction of optical signal propagation, each segment of the plurality of segments characterized by at least one width, at least one of the segments characterized by at least two widths; and
iteratively optimizing a device design starting with the initial device design by:
generating a smoothed geometry of the device design;
simulating a functionality of the device utilizing the smoothed geometry of the device design; and
utilizing an optimization algorithm on said widths characterizing said segments.
2 . A method according to claim 1 wherein generating the smoothed geometry of the device design comprises spline interpolation.
3 . A method according to claim 1 wherein iteratively optimizing the device design is performed in accordance with the fabrication design rules.
4 . A method according to claim 3 wherein the fabrication design rules comprise a minimum feature size.
5 . A method according to claim 3 wherein the fabrication design rules comprise a minimum feature size substantially equal to 200 nm.
6 . A method according to claim 1 wherein the optimization algorithm comprises at least one of a particle swarm optimization algorithm and a genetic algorithm.
7 . A method according to claim 6 wherein simulating a functionality of the device comprises determining at least one figure of merit (FOM), wherein iteratively optimizing the device design comprises evaluating optimization criteria with use of the at least one FOM, and for each iteration of said iteratively optimizing for which optimization criteria has not been met, modifying at least one of said widths characterizing said segments according to the optimization algorithm.
8 . A method according to claim 7 wherein simulating a functionality of the device comprises simulating the electromagnetic response of the device using at least one of a finite difference time domain (FDTD) method, beam propagation, and eigenmode expansion.
9 . A method according to claim 1 wherein a first width of each of the at least two widths defines a width of a core material, and a second width of each of the at least two widths defines a width of a material surrounding the core material.
10 . A method according to claim 9 wherein generating the smoothed geometry of the device design comprises spline interpolation applied to geometries of each of the two materials.
11 . A method according to claim 1 wherein generating the smoothed geometry of the device design comprises performing at least one of optical proximity correction and device fabrication simulation.
12 . A method of designing a photonic device, the method comprising:
identifying fabrication design rules of a fabrication process;
generating an initial device design by determining, with use of constraints of the fabrication design rules, a plurality of I/O ports and segments along a direction of optical signal propagation, each segment of the plurality of segments characterized by at least one width; and
iteratively optimizing a device design starting with the initial device design by:
generating a smoothed geometry of the device design with use of at least one of optical proximity correction and device fabrication simulation;
simulating a functionality of the device utilizing the smoothed geometry of the device design; and
utilizing an optimization algorithm on said widths characterizing said segments.
13 . A method according to claim 12 wherein generating the smoothed geometry of the device design comprises spline interpolation.
14 . A method according to claim 12 wherein iteratively optimizing the device design is performed in accordance with the fabrication design rules.
15 . A method according to claim 14 wherein the fabrication design rules comprise a minimum feature size.
16 . A method according to claim 14 wherein the fabrication design rules comprise a minimum feature size substantially equal to 200 nm.
17 . A method according to claim 12 wherein the optimization algorithm comprises at least one of a particle swarm optimization algorithm and a genetic algorithm.
18 . A method according to claim 12 wherein simulating a functionality of the device comprises determining at least one figure of merit (FOM), wherein iteratively optimizing the device design comprises evaluating optimization criteria with use of the at least one FOM, and for each iteration of said iteratively optimizing for which optimization criteria has not been met, modifying at least one of said widths characterizing said segments according to the optimization algorithm.
19 . A method according to claim 18 wherein simulating a functionality of the device comprises simulating the electromagnetic response of the device using at least one of a finite difference time domain (FDTD) method, beam propagation, and eigenmode expansion.