IP Library Granted Patent US 9,472,662
Granted Patent B2
US 9,472,662 · App. 14/870,333 · Granted Oct 18, 2016

Bidirectional power transistor with shallow body trench

Inventors: Evgueniy Stefanov (Vieille Toulouse, FR); Edouard Denis De Fresart (Tempe, AZ); Moaniss Zitouni (Gilbert, AZ)
Assignee: Freescale Semiconductor, Inc.
H01L29/7825H01L27/088H01L29/66704
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Quick Facts
Patent No.
US 9,472,662
App. No.
14/870,333
Granted
Oct 18, 2016
Kind
B2
Abstract

A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. An electrical path can be selectively enabled or disabled to allow current to flow in opposite directions through a body located laterally between the first and second vertical trenches. A shallow trench, more shallow than the first vertical trench and the second vertical trench is located between the first vertical trench and the second vertical trench and extend in the vertical direction from the top layer of the stack into the body, beyond an upper boundary of the body. The body is provided with a dopant, the concentration of the dopant is at least one order of magnitude higher in a region adjacent to the shallow trench than near the first vertical trench and the second vertical trench.

Claims (39)

1. A bi-directional trench field effect power transistor, comprising:

a substrate with a substrate top surface;

a layer stack extending over the substrate top surface, in which stack a first vertical trench and a second vertical trench are present, each of said vertical trenches extending in a vertical direction from a top layer of the stack towards the substrate;

a first current terminal and a second current terminal, the first current terminal being situated, in said vertical direction, below the second current terminal and the second current terminal being situation on or above the top layer; and

an electrical path which can be selectively enabled or disabled to allow current to flow in a first direction or a second direction, opposite to the first direction, between the first current terminal and the second current terminal, the electrical path comprising:

a body located laterally between the first and second vertical trenches and vertically between said first current terminal and said second current terminal;

a first drift region located, in said vertical direction, between the body and the first current terminal;

a second drift region located, in said vertical direction, between the body and the second current terminal;

a shallow trench, more shallow than the first vertical trench and the second vertical trench, the shallow trench being located between the first vertical trench and the second vertical trench and extending in the vertical direction from the top layer of the stack into the body, beyond an upper boundary of the body; and

the body is provided with a dopant, the concentration of said dopant being at least one order of magnitude higher in a region adjacent to the shallow trench than near the first vertical trench and the second vertical trench.

2. A power transistor as claimed in claim 1 , wherein the shallow trench has a bottom part and said region surrounds said bottom part.

3. A power transistor as claimed in claim 1 , wherein the shallow trench from said top layer until a shallow trench bottom, the shallow trench bottom located above a lower boundary of said body, and a region of the body with the highest concentration of said dopant is located below the shallow trench bottom and above said lower boundary.

4. A power transistor as claimed in claim 3 , wherein the concentration of said dopant in said regions is at least 2 orders of magnitude higher in said region than adjacent to the vertical trenches.

5. A power transistor as claimed in claim 1 , wherein the shallow trench is filled with a dielectric material.

6. A power transistor as claimed in claim 1 , wherein at least a part of the shallow trench is provided with a dopant of the same conductivity type as the body.

7. A power transistor as claimed in claim 5 , wherein the shallow trench comprises:

sidewalls lined with a dielectric material in a lower part extending from the upper boundary of the body into the body bottom until the bottom, and

a space extending between said sidewalls, which is filled with a semiconductor material of the same conductivity type as the dopant of in the body.

8. A power transistor as claimed in claim 7 , wherein the semiconductor material is doped polysilicon.

9. A power transistor as claimed in claim 1 , wherein the shallow trench comprises an upper part extending from the top layer until the upper boundary of the body, said upper part electrically isolating the part of the trench below the upper boundary of the body from the second drift region and the second current terminal.

10. A power transistor as claimed in claim 9 , wherein the upper part is filled with a dielectric.

11. A power transistor as claimed in claim 1 , wherein the bottom of said shallow trench is lined with a layer of a silicide provided with a dopant of the same conductivity type as the dopant body.

12. A power transistor as claimed in claim 1 , wherein the first vertical trench and the second vertical trench are spaced, in said lateral direction, between 1 to 3 micron from each other.

13. A power transistor as claimed in claim 1 , wherein the shallow trench is less than 3 micron deep.

14. A power transistor as claimed in claim 13 , wherein the shallow trench is more than 1 micron deep.

15. A power transistor as claimed in claim 1 , wherein the width of the shallow trench is less than 0.7 times the distance between the first vertical trench and the second vertical trench.

16. A power transistor as claimed in claim 1 , comprising separate contacts connected to individually control the voltage and/or current of the gate electrode, the first current terminal, the second current terminal, and the body.

17. A power transistor as claimed in claim 16 , comprising further separate contacts connected to individually control the voltage of the lower shield plate and the gate.

18. A power transistor as claimed in claim 1 , comprising a elongated vertical trench enclosure which, in a plane parallel to the substrate top-surface, encloses the electrical path, the first vertical trench and the second vertical trench being part of the elongated vertical trench enclosure.

19. A method of manufacturing a power transistor as claimed in claim 1 , the method comprising:

providing on a substrate a layer stack extending over said substrate, and providing the layer stack with a first vertical trench and a second vertical trench, each of said vertical trenches extending in a vertical direction from a top layer of the stack towards the substrate;

providing a second current terminal on or above the top layer and a first current terminal, in said vertical direction, below the second current terminal; and

providing an electrical path which can be selectively enabled or disabled to allow current to flow between the first current terminal and the second current terminal, providing the electrical path comprising:

providing a body located in said vertical direction between said first current terminal and said second current terminal and laterally between the first and second vertical trenches;

providing a first drift region, in said vertical direction, between the body and the first current terminal;

providing a second drift region, in said vertical direction, between the body and the second current terminal;

providing in the top layer a shallow trench between the first vertical trench and the second vertical trench, the shallow trench being shallow relative to the first vertical trench and the second vertical trench and extending in the vertical direction from the top layer of the stack into the body beyond an upper boundary of the body;

providing through said trench a dopant into a region of the body adjacent to the shallow trench, with a concentration of at least one order of magnitude higher than a dopant concentration near the first vertical trench and the second vertical trench;

and performing further operations to finalize the power transistor.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2015
From: STEFANOV, EVGUENIY; DE FRESART, EDOUARD DENIS; ZITOUNI, MOANISS
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 036690/0979 →
Priority Claims (1)
WO PCT/IB2015/001363 · Feb 23, 2015 · international
Continuity (1)
Related Publication 20160247916A1 · Aug 25, 2016