IP Library Granted Patent US 9,910,798
Granted Patent B2
US 9,910,798 · App. 14/874,998 · Granted Mar 6, 2018

Storage controller cache memory operations that forego region locking

Inventors: Horia Cristian Simionescu (Milpitas, CA); Timothy E. Hoglund (Colorado Springs, CO); Sridhar Rao Veerla (Bangalore, IN); Panthini Pandit (Bangalore, IN); Gowrisankar Radhakrishnan (Colorado Springs, CO)
Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
G06F13/28G06F3/0613G06F3/0647G06F3/0659G06F3/0689G06F12/0893G06F2212/1016G06F2212/60
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Quick Facts
Patent No.
US 9,910,798
App. No.
14/874,998
Granted
Mar 6, 2018
Kind
B2
Abstract

Methods and structure for managing cache memory for a storage controller. One exemplary embodiment a Redundant Array of Independent Disks (RAID) storage controller. The storage controller includes an interface operable to receive Input/Output (I/O) requests from a host, a Direct Memory Access (DMA) module, a memory comprising cache data for a logical volume, and a control unit. The control unit is able to generate Scatter Gather Lists (SGLs) that indicate the location of cache data for incoming read requests. Each SGL is stored in the memory, and at least one SGL points to cache data that is no longer indexed by the cache. The control unit is also able to service an incoming read request based on the SGL, by directing the DMA module to transfer the cache data that is no longer indexed to the host.

Claims (58)

1. A Redundant Array of Independent Disks (RAID) storage controller comprising:

an interface that receives Input/Output (I/O) requests from a host;

a Direct Memory Access (DMA) module;

a memory comprising buffer segments that store data for a logical volume, and further comprising cache entries that correlate buffer segments with Logical Block Addresses (LBAs) of the logical volume; and

a control unit that detects an incoming read request, queries the cache entries to identify buffer segments storing data for the read request, generates a Scatter Gather List (SGL) indicating the identified buffer segments, and directs the DMA module to transfer data to the host based on the SGL,

wherein the control unit further detects an incoming write request that updates LBAs referenced by the read request, updates a cache entry by eliminating a reference to one of the identified buffer segments and adding a new reference to a new buffer segment, and after the cache entry has been updated, prevents the identified buffer segment from being overwritten before the DMA module has finished reading data from the identified buffer segment.

2. The system of claim 1 , wherein:

the SGL comprises multiple Scatter Gather Entries (SGEs) that each indicate a buffer segment storing data for the read request.

3. The system of claim 1 , wherein:

a cache manager utilizes a hash table to index the cache entries.

4. The system of claim 3 , wherein:

entries in the hash table are ordered by a combination of logical volume identifier and strip number for a logical volume.

5. The system of claim 1 , wherein:

the control unit generates multiple SGLs for the read request, and links the SGLs together via chain Scatter Gather Entries (SGEs) within the SGLs.

6. The system of claim 1 , wherein:

the control unit populates the new buffer segment with data for the incoming write request.

7. The system of claim 1 , wherein:

the control unit enables overwriting of the identified buffer segment by deallocating the identified buffer segment.

8. A method for operating a Redundant Array of Independent Disks (RAID) storage controller, the method comprising:

receiving a read request directed to Logical Block Addresses (LBAs) of a logical volume;

querying cache entries in memory that identify buffer segments in the memory which are correlated with the LBAs, wherein the buffer segments store data for the logical volume;

generating a Scatter Gather List (SGL) indicating the identified buffer segments;

directing a Direct Memory Access (DMA) module to transfer data to the host based on the SGL;

detecting an incoming write request that updates LBAs referenced by the read request;

updating a cache entry based on the write request by eliminating a reference to one of the identified buffer segments and adding a reference for a new buffer segment storing the updated LBAs; and

in response to updating the cache entry, preventing the identified buffer segment from being overwritten before the DMA module has finished reading data from the identified buffer segment.

9. The method of claim 8 , wherein:

the SGL comprises multiple Scatter Gather Entries (SGEs) that each indicate a buffer segment storing data for the read request.

10. The method of claim 8 , further comprising:

utilizing a hash table to index the cache entries.

11. The method of claim 10 , wherein:

entries in the hash table are ordered by a combination of logical volume identifier and strip number for a logical volume.

12. The method of claim 8 , further comprising:

generating multiple SGLs for the read request; and

linking the SGLs together via chain Scatter Gather Entries (SGEs) within the SGLs.

13. The method of claim 8 , further comprising:

populating the new buffer segment with data for the incoming write request.

14. The method of claim 8 , further comprising:

enabling overwriting of the identified buffer segment by deallocating the identified buffer segment.

15. A non-transitory computer readable medium embodying programmed instructions which, when executed by a processor, enable the processor to:

receive a read request directed to Logical Block Addresses (LBAs) of a logical volume;

query cache entries in memory that identify buffer segments in the memory which are correlated with the LBAs, wherein the buffer segments store data for the logical volume;

generate a Scatter Gather List (SGL) indicating the identified buffer segments;

direct a Direct Memory Access (DMA) module to transfer data to the host based on the SGL;

detect an incoming write request that updates LBAs referenced by the read request;

update a cache entry based on the write request by eliminating a reference to one of the identified buffer segments and adding a reference for a new buffer segment storing the updated LBAs; and

in response to updating the cache entry, prevent the identified buffer segment from being overwritten before the DMA module has finished reading data from the identified buffer segment.

16. The medium of claim 15 , wherein:

the SGL comprises multiple Scatter Gather Entries (SGEs) that each indicate a buffer segment storing data for the read request.

17. The medium of claim 15 , wherein the instructions further direct the processor to:

utilize a hash table to index the cache entries.

18. The medium method of claim 17 , wherein:

entries in the hash table are ordered by a combination of logical volume identifier and strip number for a logical volume.

19. The medium of claim 15 , wherein the instructions further direct the processor to:

generate multiple SGLs for the read request; and

link the SGLs together via chain Scatter Gather Entries (SGEs) within the SGLs.

20. The method of claim 15 , wherein the instructions further direct the processor to:

populate the new buffer segment with data for the incoming write request.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: SIMIONESCU, HORIA CRISTIAN; HOGLUND, TIMOTHY E; VEERLA, SRIDHAR RAO; PANDIT, PANTHINI; RADHAKRISHNAN, GOWRISANKAR
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036728/0362 →
Continuity (1)
Related Publication 20170097909A1 · Apr 6, 2017