Semiconductor device

1. A semiconductor device comprising one parallel transistor in which a plurality of vertical transistors disposed in an active region on a semiconductor substrate are connected in parallel, wherein the parallel transistor comprises:

a plurality of semiconductor pillars protruding out in a direction perpendicular to a main surface of the semiconductor substrate;

a lower diffusion layer disposed below the plurality of semiconductor pillars;

a plurality of upper diffusion layers, disposed respectively at the top of the plurality of semiconductor pillars; and

a gate electrode disposed over the side surfaces, in their entirety, of the plurality of semiconductor pillars, with the interposition of a gate insulating film;

and wherein the plurality of upper diffusion layers are connected to one upper contact plug disposed on the plurality of upper diffusion layers, and wherein the one upper contact plug is connected to a wiring line disposed on the one upper contact plug.

2. The semiconductor device as claimed in claim 1 , wherein each of the plurality of upper diffusion layers comprises:

a diffusion layer disposed at the top of the semiconductor pillar; and

a silicon plug connected to an upper surface of said diffusion layer.

3. The semiconductor device as claimed in claim 1 , comprising an insulating film provided at the peripheries of the plurality of semiconductor pillars, wherein the lower diffusion layer and the gate electrode are electrically insulated from one another by means of said insulating film.

4. The semiconductor device as claimed in claim 1 , wherein the lower diffusion layer is connected to a lower contact plug.

5. A semiconductor device comprising:

an element isolation region disposed in a main surface of a semiconductor substrate;

a first active region and a second active region which are enclosed by the element isolation region and are adjacent to one another in a first direction; and

an intermediate element isolation region sandwiched between the first active region and the second active region;

wherein the first active region comprises:

a first semiconductor pillar adjacent to the intermediate element isolation region;

a first upper diffusion layer located at the top of the first semiconductor pillar;

a second semiconductor pillar adjacent, in the first direction, to the first semiconductor pillar;

a second upper diffusion layer located at the top of the second semiconductor pillar;

a continuous first gate electrode enclosing the peripheries of the first semiconductor pillar and the second semiconductor pillar;

a first lower diffusion layer disposed below the first and second semiconductor pillars;

the second active region comprises:

a third semiconductor pillar adjacent to the intermediate element isolation region;

a third upper diffusion layer located at the top of the third semiconductor pillar;

a fourth semiconductor pillar adjacent, in the first direction, to the third semiconductor pillar;

a fourth upper diffusion layer located at the top of the fourth semiconductor pillar;

a continuous second gate electrode enclosing the peripheries of the third semiconductor pillar and the fourth semiconductor pillar;

a second lower diffusion layer disposed below the third and fourth semiconductor pillars, wherein the first and second lower diffusion layers are connected respectively to first and second lower contact plugs; and

the intermediate element isolation region comprises:

a dummy pillar extending in the first direction, spanning between the first active region and the second active region; and

a power-feed gate electrode enclosing the periphery of the dummy pillar;

the first gate electrode and the second gate electrode are each connected to the power-feed gate electrode;

the first upper diffusion layer and the second upper diffusion layer are connected to one first upper contact plug; and

the third upper diffusion layer and the fourth upper diffusion layer are connected to one second upper contact plug.

6. The semiconductor device as claimed in claim 5 , wherein:

the semiconductor device additionally comprises an insulating film provided at the peripheries of the first to fourth semiconductor pillars;

the first lower diffusion layer and the first gate electrode are electrically insulated from one another by means of the insulating film; and

the second lower diffusion layer and the second gate electrode are electrically insulated from one another by means of the insulating film.

7. A semiconductor device comprising:

an element isolation region disposed in a main surface of a semiconductor substrate; and

a first active region and a second active region which are enclosed by the element isolation region and are adjacent to one another in a first direction, with the interposition of an intermediate element isolation region;

wherein the first active region comprises:

first and second semiconductor pillars which are adjacent to the intermediate element isolation region and are adjacent to one another in a second direction orthogonal to the first direction;

first and second upper diffusion layers located respectively at the top of the first and second semiconductor pillars; and

a continuous first gate electrode enclosing the peripheries of the first semiconductor pillar and the second semiconductor pillar;

the second active region comprises:

third and fourth semiconductor pillars which are adjacent to the intermediate element isolation region and are adjacent to one another in the second direction orthogonal to the first direction;

third and fourth upper diffusion layers located respectively at the top of the third and fourth semiconductor pillars; and

a continuous second gate electrode enclosing the peripheries of the third semiconductor pillar and the fourth semiconductor pillar; and

the intermediate element isolation region comprises:

a dummy pillar extending in the first direction, spanning between the first active region and the second active region; and

a power-feed gate electrode enclosing the periphery of the dummy pillar;

the first gate electrode and the second gate electrode are each connected to the power-feed gate electrode; and

the first upper diffusion layer to the fourth upper diffusion layer are connected to one upper contact plug.

8. The semiconductor device as claimed in claim 7 , wherein the first active region and the second active region are formed from semiconductor regions having the same conduction type.

9. The semiconductor device as claimed in claim 8 , wherein:

the first active region is provided with a first lower diffusion layer disposed below the first and second semiconductor pillars;

the second active region is provided with a second lower diffusion layer disposed below the third and fourth semiconductor pillars;

the semiconductor device additionally comprises an insulating film provided at the peripheries of the first to fourth semiconductor pillars;

the first lower diffusion layer and the first gate electrode are electrically insulated from one another by means of the insulating film; and

the second lower diffusion layer and the second gate electrode are electrically insulated from one another by means of the insulating film.

10. The semiconductor device as claimed in claim 9 , wherein the first and second lower diffusion layers are connected respectively to first and second lower contact plugs.

11. The semiconductor device as claimed in claim 7 , wherein the first active region and the second active region are formed from semiconductor regions having mutually different conduction types.

12. The semiconductor device as claimed in claim 11 , wherein:

the first active region is provided with a first lower diffusion layer disposed below the first and second semiconductor pillars;

the second active region is provided with a second lower diffusion layer disposed below the third and fourth semiconductor pillars;

the semiconductor device additionally comprises an insulating film provided at the peripheries of the first to fourth semiconductor pillars;

the first lower diffusion layer and the first gate electrode are electrically insulated from one another by means of the insulating film; and

the second lower diffusion layer and the second gate electrode are electrically insulated from one another by means of the insulating film.

13. The semiconductor device as claimed in claim 12 , wherein the first and second lower diffusion layers are connected respectively to first and second lower contact plugs.

14. The semiconductor device as claimed in claim 12 , wherein:

the first active region is formed from a semiconductor region having a first conduction type;

the second active region is formed from a semiconductor region having a second conduction type which is different from the first conduction type;

the first and second upper diffusion layers and the first lower diffusion layer are formed from diffusion layers having the second conduction type; and

the third and fourth upper diffusion layers and the second lower diffusion layer are formed from diffusion layers having the first conduction type.