IP Library Granted Patent US 9,641,362
Granted Patent B2
US 9,641,362 · App. 14/891,454 · Granted May 2, 2017

N-wire two-level digital interface

Inventor: Kimmo Koli (Turku, FI)
Assignee: OPTIS CIRCUIT TECHNOLOGY, LLC
H04L25/4917H04B7/06H04L25/0272H04L25/0292
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,641,362
App. No.
14/891,454
Granted
May 2, 2017
Kind
B2
Abstract

A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node.

Claims (37)

1. A receiver comprising:

N input terminals, where N is any integer exceeding two;

a common node; and

N detection stages, each of the N detection stages including:

a resistive element, each of the resistive elements coupled between the common node and a respective one of the N input terminals; and

a comparator, each of the comparators having a first input coupled directly to a respective one of the N input terminals and a second input coupled directly to the common node, wherein the resistive element of each of the N detection stages has a same resistance value.

2. The receiver as claimed in claim 1 , further comprising:

a decoder coupled to comparator outputs of the N detection stages and configured to determine a received symbol dependent on states of the comparator outputs.

3. The receiver as claimed in claim 2 , wherein the decoder comprises a first look-up table for mapping the states of the comparator outputs to the received symbol.

4. The receiver as claimed in claim 1 , wherein N is one of: three, four and five.

5. A signaling system comprising:

a transmitter configured to generate N signaling voltages applied to wires of an N-wire interface, respectively, each of the N signaling voltages being indicative of a different one of N bits to be transmitted, and having a value selected from two values; and

a receiver having N input terminals, a common node, and N detection stages, where N is any integer exceeding two, each of the N detection stages including:

a resistive element, each of the resistive elements coupled between the common node and a respective one of the N input terminals; and

a comparator, each of the comparators having a first input coupled directly to a respective one of the N input terminals and a second input coupled directly to the common node,

wherein the resistive element of each of the N detection stages has a same resistance value, and the N input terminals are coupled to the wires of the N-wire interface, respectively.

6. The signaling system as claimed in claim 5 , further comprising an encoder configured to map a symbol to the N bits to be transmitted.

7. The signaling system as claimed in claim 6 , wherein the encoder comprises a second look-up table for mapping the symbol to the N bits to be transmitted.

8. The signaling system as claimed in claim 5 , wherein N is three, and wherein two of the N signaling voltages have a first value and a third one of the N signaling voltages has a second value, which is different from the first value.

9. The signaling system as claimed in claim 5 , wherein N is four, and wherein at least two of the N signaling voltages have a first value and the at least one other of the N signaling voltages has a second value, which is different from the first value.

10. The signaling system as claimed in claim 5 , wherein N is five, and wherein three of the N signaling voltages have a first value and two of the N signaling voltages have a second value, which is different from the first value.

11. A method of operating a signaling system, the method comprising:

providing a receiver having N input terminals, a common node, and N detection stages, where N is any integer exceeding two, each of the N detection stages including:

a resistive element, each of the resistive elements coupled between the common node and a respective one of the N input terminals; and

a comparator, each of the comparators having a first input coupled directly to a respective one of the N input terminals and a second input coupled directly to the common node, wherein the resistive element of each of the N detection stages has a same resistance value;

selecting N signaling voltages, wherein each of the N signaling voltages is selected from two values;

delivering the N signaling voltages to the N input terminals of the receiver, respectively; and

determining a received symbol dependent on the N signaling voltages.

12. The method as claimed in claim 11 , wherein N is three, and wherein two of the N signaling voltages have a first value and a third one of the N signaling voltages has a second value, which is different from the first value.

13. The method as claimed in claim 11 , wherein N is four, wherein at least two of the N signaling voltages have a first value and at least one other of the N signaling voltages has a second value, which is different from the first value.

14. The method as claimed in claim 11 , wherein N is five, and wherein three of the N signaling voltages have a first value and two of the N signaling voltages have a second, which is value different from the first value.

15. A wireless communication device comprising:

a transmitter configured to generate N signaling voltages applied to wires of an N-wire interface, respectively, each of the N signaling voltages being indicative of a different one of N bits to be transmitted, and having a value selected from two values; and

a receiver having N input terminals, a common node, and N detection stages, where N is any integer exceeding two, each of the N detection stages including:

a resistive element, each of the resistive elements coupled between the common node and a respective one of the N input terminals; and

a comparator, each of the comparators having a first input coupled directly to a respective one of the N input terminals and a second input coupled directly to the common node,

wherein the resistive element of each of the N detection stages has a same resistance value, and the N input terminals are coupled to the wires of the N-wire interface, respectively.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2019
From: OPTIS CIRCUIT TECHNOLOGY, LLC,
To: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
Reel/Frame 048529/0510 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: ST-ERICSSON SA, EN LIQUIDATION
To: OPTIS CIRCUIT TECHNOLOGY, LLC
Reel/Frame 040821/0169 →
STATUS CHANGE-ENTITY IN LIQUIDATION Recorded Feb 2, 2016
From: ST-ERICSSON SA
To: ST-ERICSSON SA, EN LIQUIDATION
Reel/Frame 037739/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2015
From: KOLI, KIMMO
To: ST-ERICSSON SA
Reel/Frame 037070/0373 →
Priority Claims (1)
EP 13172354 · Jun 17, 2013 · regional
Continuity (1)
Related Publication 20160127158A1 · May 5, 2016