Method and apparatus for selective write assist using shared boost capacitor

1. A memory device, comprising:

a plurality of columns of memory cells;

a plurality of write assist circuits coupled to the plurality of columns of memory cells;

a shared boost capacitor shared by the plurality of write assist circuits, the shared boost capacitor having a first terminal and a second terminal; and

a boost switch circuit configured to selectively couple one or more first write assist circuits from among the plurality of write assist circuits to the first terminal of the shared boost capacitor,

wherein the boost switch circuit comprises:

a logic gate connected to the second terminal of the shared boost capacitor, the logic gate being configured to:

receive an input from each one of the plurality of write assist circuits resulting in a plurality of inputs, and

toggle a voltage on the second terminal of the shared boost capacitor to generate a negative voltage on the first terminal of the shared boost capacitor in response to the plurality of inputs indicating one or more first memory cells from among the plurality of columns of memory cells need write assistance; and

a plurality of write assist enable transistors, each write assist enable transistor corresponding to one of the plurality of write assist circuits and independently controllable by a corresponding write assist control line, each write assist enable transistor configured to selectively connect and disconnect the negative voltage on the first terminal of the shared boost capacitor to bitlines of the corresponding write assist circuit based on a control signal on the corresponding write assist control line;

wherein the selectively coupled one or more first write assist circuits are configured to cause the one or more first memory cells from among the plurality of columns of memory cells to change their logical states during a write operation using the negative voltage.

2. The memory device of claim 1 , wherein each write assist circuit from among the plurality of write assist circuits is coupled to a corresponding column from among the plurality of columns of memory cells.

3. The memory device of claim 2 , wherein the shared boost capacitor is configured to drive the corresponding column below zero volts.

4. The memory device of claim 1 ,

wherein the plurality of columns of memory cells is coupled to a plurality of bit lines, and

wherein the boost switch circuit is configured to couple the bitlines from among the plurality of bitlines of the selectively coupled one or more first write assist circuits to the shared boost capacitor.

5. The memory device of claim 4 , wherein the shared boost capacitor is configured to drive the bitlines below zero volts.

6. The memory device of claim 1 , wherein the boost switch circuit is configured to selectively couple a first write assist circuit from among the one or more first write assist circuits to the shared boost capacitor in response to a first control signal being at a first logical value, and

wherein the boost switch circuit is configured to selectively couple a second write assist circuit from among the one or more first write assist circuits to the shared boost capacitor in response to a second control signal being at the first logical value, and

wherein the boost switch circuit is further configured to simultaneously couple the first write assist circuit and the second write assist circuit to the shared boost capacitor in response to the first control signal and the second control signal being at the first logical value.

7. The memory device of claim 1 , wherein the boost switch circuit is configured to selectively couple the one or more first write assist circuits to the shared boost capacitor in response to a first control signal being at a first logical value, and

wherein the boost switch circuit is configured to selectively decouple one or more second write assist circuits from among the plurality of write assist circuits from the shared boost capacitor in response to a second control signal being at a second logical value.

8. The memory device of claim 1 , wherein the boost switch circuit is further configured to decouple one or more second write assist circuits from among the plurality of write assist circuits from the first terminal of the shared boost capacitor.

9. The memory device of claim 1 , wherein the logic gate comprises:

a logical NOR gate having an output directly coupled to the shared boost capacitor.

10. A memory device, comprising:

a plurality of memory cells arranged into a plurality of rows and a plurality of columns;

a row decoder configured to access a row from among the plurality of rows;

a column decoder configured to access a column of the row from among the plurality of columns to select a memory cell from among the plurality of memory cells;

column circuitry configured to write data to the selected memory cell, the column circuitry comprising:

a plurality of write assist circuits coupled to the plurality of memory cells;

a shared boost capacitor shared by the plurality of write assist circuits, the shared boost capacitor having a first terminal and a second terminal; and

a boost switch circuit configured to selectively couple a write assist circuit corresponding to the selected memory cell from among the plurality of write assist circuits to the first terminal of the shared boost capacitor to provide write assistance to the selected memory cell,

wherein the boost switch circuit comprises;

a logic gate connected to the second terminal of the shared boost capacitor, the logic gate being configured to:

receive an input from each one of the plurality of write assist circuits resulting in a plurality of inputs, and

toggle a voltage on the second terminal of the shared boost capacitor to generate a negative voltage on the first terminal of the shared boost capacitor in response to the plurality of inputs indicating one or more first memory cells from among the plurality of columns of memory cells need write assistance; and

a plurality of write assist enable transistors, each write assist enable transistor corresponding to one of the plurality of write assist circuits and independently controllable by a corresponding write assist control line, each write assist enable transistor configured to selectively connect and disconnect the negative voltage on the first terminal of the shared boost capacitor to bitlines of the corresponding write assist circuit based on a control signal on the corresponding write assist control line;

wherein the selectively coupled write assist circuit is configured to cause the selected memory cell to change its logical state during a write operation using the negative voltage.

11. The memory device of claim 10 , wherein the row decoder is configured to access the row by asserting one or more corresponding wordlines from among a plurality of wordlines.

12. The memory device of claim 10 , wherein the column decoder is configured to access the column by asserting one or more corresponding bitlines of the selectively coupled write assist circuit.

13. The memory device of claim 12 , wherein the boost switch circuit is configured to selectively couple the one or more corresponding bitlines to the shared boost capacitor to provide write assistance to the selected memory cell.

14. The memory device of claim 12 , wherein the shared boost capacitor is configured to drive the one or more corresponding bitlines below zero volts.

15. The memory device of claim 10 , wherein the boost switch circuit is configured to selectively couple the write assist circuit to the shared boost capacitor in response to a first control signal being at a first logical value or to decouple the write assist circuit from the shared boost capacitor in response to the first control signal being at a second logical value.

16. The memory device of claim 15 , wherein the boost switch circuit comprises:

a transistor configured to selectively couple the write assist circuit to the shared boost capacitor when the first control signal is at the first logical value or to decouple the write assist circuit from the shared boost capacitor when the first control signal is at the second logical value.

17. A method of writing data to a memory cell from among a plurality of memory cells, the plurality of memory cells being arranged into a plurality of rows and a plurality of columns, the method comprising:

accessing a row from among the plurality of rows;

accessing a column of the row from among the plurality of columns to select the memory cell;

selectively coupling, by a write assist enable transistor, a write assist circuit corresponding to the memory cell from among the plurality of write assist circuits to a first terminal of a shared boost capacitor to provide write assistance to the memory cell, the shared boost capacitor being shared by the plurality of write assist circuits;

receiving by a logic gate connected to the shared boost capacitor, a plurality of inputs corresponding to the plurality of write assist circuits;

toggling, by the logic gate, a voltage on the second terminal of the shared boost capacitor to generate a negative voltage on the first terminal of the shared boost capacitor in response to the plurality of inputs indicating one or more first memory cells from among the plurality of columns of memory cells need write assistance; and

writing data to the memory cell utilizing the write assistance, the writing comprising:

causing the memory cell to change its logical state during a write operation using the negative voltage.

18. The method of claim 17 , wherein the accessing the row comprises:

accessing the row by asserting one or more corresponding wordlines from among a plurality of wordlines, and

wherein the accessing the column comprises:

accessing the column by asserting one or more corresponding bitlines from among a plurality of bitlines.

19. The method of claim 18 , wherein the selectively coupling comprises:

coupling the one or more corresponding bitlines of the selectively coupled write assist circuit to the shared boost capacitor to provide the write assistance to the memory cell.

20. The method of claim 19 , wherein the coupling the one or more corresponding bitlines comprises:

coupling the one or more corresponding bitlines of the selectively coupled write assist circuit to the shared boost capacitor to drive the one or more corresponding bitlines below zero volts.