Systems and methods for efficient flash memory access
View Patent ↗Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.
1. A system for accessing a flash memory device, the system comprising:
a first encoder circuit operable to apply a first encoding algorithm to a user data set to yield a first number of first algorithm codewords, wherein each of the first number of the first algorithm codewords includes a second number of elements;
a second encoder circuit operable to apply a second encoding algorithm to a combination of the first number of the first algorithm codewords to yield a second number of sets of a third number of voltage values; wherein each of the sets of the third number of voltage values represents corresponding elements of each of the first number of the first algorithm codewords; and
a write circuit operable to apply voltages indicated by each of the third number of voltage values to respective flash memory cells.
2. The system of claim 1 , wherein the first encoding algorithm is a low density parity check algorithm, and wherein the first algorithm codewords are low density parity check algorithm codewords.
3. The system of claim 1 , wherein the first number is five, and wherein the third number is three, wherein the flash memory cells are two-bit memory cells, and wherein each of the three voltage values is selected from a group consisting of: 0, 1, 2, and 3.
4. The system of claim 1 , wherein each of the elements of the second number of elements are indicated at positions of the first algorithm codewords.
5. The system of claim 1 , wherein the system is implemented as part of an integrated circuit.
6. The system of claim 1 , wherein the system further comprises:
a data read circuit operable to compare voltages read from a group of flash memory cells with a first threshold value to yield a binary output set, wherein each of the flash memory cells is programmed to hold two or more bits;
a first data decoding circuit operable to decode the binary output set to yield at least one of the first algorithm codewords; and
a second data decoding circuit operable to decode the at least one of the first algorithm codewords.
7. The system of claim 6 , wherein the binary output set is a first binary output set wherein the at least one of the first algorithm codewords includes a first algorithm codeword, wherein the data read circuit is further operable to compare voltages read from the group of flash memory cells with a second threshold value to yield a second binary output set, and wherein the first data decoding circuit is further operable to decode the second binary output set to yield at least a second and third of the first algorithm codewords.
8. The system of claim 7 , wherein the data read circuit is further operable to compare voltages read from the group of flash memory cells with a third threshold value to yield a third binary output set, and wherein the first data decoding circuit is further operable to decode the third binary output set to yield at least a fourth and a fifth of the first algorithm codewords.
9. The system of claim 6 , wherein the second data decoding circuit is a low density parity check decoding circuit.
10. The system of claim 9 , wherein five low density parity check codewords are represented as voltages in the a group of flash memory cells.
11. The system of claim 9 , wherein each three flash memory cells of the group of flash memory cells are programmed with voltages representing a single element from each of the five low density parity check codewords.
12. A system for accessing a flash memory device, the system comprising:
a data read circuit operable to compare voltages read from a group of flash memory cells with a first threshold value to yield a binary output set, wherein each of the flash memory cells is programmed to hold two or more bits;
a first data decoding circuit operable to decode the binary output set to yield at least one encoded codeword; and
a second data decoding circuit operable to decode the at least one encoded codeword.
13. The system of claim 12 , wherein the binary output set is a first binary output set, wherein the at least one encoded codeword includes a first encoded codeword, wherein the data read circuit is further operable to compare voltages read from the group of flash memory cells with a second threshold value to yield a second binary output set, and wherein the first data decoding circuit is operable to decode the second binary output set to yield at least a second and third encoded codeword.
14. The system of claim 13 , wherein the data read circuit is further operable to compare voltages read from the group of flash memory cells with a third threshold value to yield a third binary output set, and wherein the first data decoding circuit is operable to decode the third binary output set to yield at least a fourth and a fifth encoded codeword.
15. The system of claim 12 , wherein the second data decoding circuit is a low density parity check decoding circuit.
16. The system of claim 15 , wherein five low density parity check codewords are represented as voltages in the a group of flash memory cells.
17. The system of claim 15 , wherein each three flash memory cells of the group of flash memory cells are programmed with voltages representing a single element from each of the five low density parity check codewords.
18. The system of claim 12 , wherein the system is implemented as part of an integrated circuit.
19. The system of claim 12 , wherein the system further comprises:
a first encoder circuit operable to apply a first encoding algorithm to a user data set to yield a first number of the encoded codewords, wherein each of the first number of encoded codewords includes a second number of elements;
a second encoder circuit operable to apply a second encoding algorithm to a combination of the first number of the encoded codewords to yield a second number of sets of a third number of voltage values; wherein each of the sets of the third number of voltage values represents corresponding elements of each of the first number of the encoded codewords; and
a write circuit operable to apply voltages indicated by each of the third number of voltage values to respective ones of the flash memory cells.
20. The system of claim 19 , wherein the first encoding algorithm is a low density parity check algorithm, and wherein the encoded codewords are low density parity check algorithm codewords.
21. The system of claim 19 , wherein the first number is five, and wherein the third number is three.