IP Library Granted Patent US 9,705,452
Granted Patent B2
US 9,705,452 · App. 14/927,880 · Granted Jul 11, 2017

Protection circuit for power amplifier

Inventors: Jun Hee Oh (Gyeonggi-do, KR); Moon Suk Jeon (Seoul, KR); Joo Min Jung (Gyeonggi-do, KR); Jung Hyun Kim (Gyeonggi-do, KR)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
H03F1/52H03F3/19H03F3/21H03F3/45071H03F2200/222H03F2200/387H03F2200/426H03F2200/451H03F2203/45116
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Quick Facts
Patent No.
US 9,705,452
App. No.
14/927,880
Granted
Jul 11, 2017
Kind
B2
Abstract

A power amplifier comprising a power stage comprises a voltage detection circuit configured to detect an output voltage of the power stage, a current detection circuit configured to detect an output current of the power stage, a control voltage generation circuit configured to generate a control voltage substantially proportional to the detected output voltage and the detected output current, and a control circuit configured to decrease an output power of the power stage when the control voltage exceeds a predetermined value.

Claims (33)

1. A power amplifier comprising a power stage, comprising:

a voltage detection circuit configured to detect an output voltage of the power stage;

a current detection circuit configured to detect an output current of the power stage;

a control voltage generation circuit configured to generate a control voltage substantially proportional to the detected output voltage and the detected output current, the control voltage being proportional to a current flowing in the control voltage generation circuit, and being provided to an output node of the control voltage generation circuit; and

a control circuit configured to decrease an output power of the power stage when the control voltage exceeds a predetermined value wherein the current flowing in the control voltage generation circuit is substantially proportional to the detected output current and the detected output voltage.

2. The power amplifier of claim 1 , wherein the control circuit decreases the output power of the power stage by decreasing a bias current to a bias node of the power stage when the control voltage exceeds the predetermined value.

3. The power amplifier of claim 1 , wherein the control circuit decreases the output power of the power stage by way of decreasing an input power to the power stage when the control voltage exceeds the predetermined value.

4. The power amplifier of claim 1 , wherein the control voltage generation circuit comprises a parallel RC (resistor-capacitor) circuit through which the current flows, the parallel RC circuit being electrically coupled to the output node of the control voltage generation circuit.

5. The power amplifier of claim 1 , wherein the current detection circuit comprises a first transistor configured to provide the control voltage generation circuit with a current substantially proportional to the detected output current, the first transistor being electrically coupled between the output node of the power stage and the output node of the control voltage generation circuit.

6. The power amplifier of claim 1 , wherein the voltage detection circuit comprises a diode set comprising one or more diodes connected in series,

wherein the diode set is configured to provide the control voltage generation circuit with a current substantially proportional to the detected output voltage when the detected output voltage exceeds a threshold voltage of the diode set, and

wherein the diode set is electrically coupled between the output node of the power stage and the output node of the control voltage generation circuit.

7. The power amplifier of claim 6 , wherein the threshold voltage of the diode set is equal to a product of a turn-on voltage of the respective one or more diodes included in the diode set and a total number of the diodes.

8. The power amplifier of claim 2 , wherein the control circuit comprises a second transistor configured to draw a current from a bias circuit of the power stage so as to reduce the bias current when the control voltage exceeds a predetermined value, the bias circuit biasing the power stage by applying the bias current to the bias node of the power stage.

9. The power amplifier of claim 3 , wherein the control circuit comprises:

a third transistor which is electrically coupled to an input node of the power stage via a first diode, the third transistor configured to decrease the input power of the power stage by drawing a current from the input node of the power stage when the control voltage exceeds the predetermined value and an input voltage of the power stage exceeds a predetermined positive value; and

a fourth transistor which is electrically coupled to the input node of the power stage via a second diode, the fourth transistor configured to decrease the input power of the power stage by supplying a current to the input node of the power stage when the control voltage exceeds the predetermined value and the input voltage of the power stage is lower than a predetermined negative value.

10. The power amplifier of claim 1 , wherein the power amplifier is a differential power amplifier.

11. A cellular mobile system, comprising:

a power amplifier comprising:

a voltage detection circuit configured to detect an output voltage of a power stage of the power amplifier;

a current detection circuit configured to detect an output current of the power stage;

a control voltage generation circuit configured to generate a control voltage substantially proportional to the detected output voltage and the detected output current, the control voltage being proportional to a current flowing in the control voltage generation circuit, and being provided to an output node of the control voltage generation circuit; and

a control circuit configured to decrease an output power of the power stage when the control voltage exceeds a predetermined value, wherein the current flowing in the control voltage generation circuit is substantially proportional to the detected output current and the detected output voltage.

12. The cellular mobile system of claim 11 , wherein the control circuit decreases the output power of the power stage by way of decreasing a bias current to a bias node of the power stage when the control voltage exceeds the predetermined value.

13. The cellular mobile system of claim 11 , wherein the control circuit decreases the output power of the power stage by way of decreasing an input power to the power stage when the control voltage exceeds the predetermined value.

14. The cellular mobile system of claim 11 , further comprising an impedance matching circuit which comprises an input matching circuit electrically coupled to an input node of the power stage and an output matching circuit electrically coupled to an output node of the power stage.

15. A method for protecting a power amplifier comprising a power stage, comprising:

detecting an output voltage of the power stage by using a voltage detection circuit and an output current of the power stage by using a current detection circuit;

generating a control voltage substantially proportional to the detected output voltage and the detected output current by using a control voltage generation circuit, the generating the control voltage comprising: generating the control voltage proportional to a current flowing in the control voltage generation circuit; and outputting the control voltage to an output node of the control voltage generation circuit wherein the current flowing in the control voltage generation circuit is substantially proportional to the detected output current and the detected output voltage; and

decreasing an output power of the power stage when the control voltage exceeds a predetermined value.

16. The method of claim 15 , wherein said decreasing the output power comprises decreasing a bias current to a bias node of the power stage when the control voltage exceeds the predetermined value.

17. The method of claim 15 , wherein said decreasing the output power comprises decreasing an input power to the power stage when the control voltage exceeds the predetermined value.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2015
From: OH, JUN-HEE; JEON, MOON-SUK; JUNG, JOO-MIN; KIM, JUNG-HYUN
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036999/0459 →
Continuity (1)
Related Publication 20170126184A1 · May 4, 2017