IP Library Granted Patent US 9,727,419
Granted Patent B2
US 9,727,419 · App. 14/935,333 · Granted Aug 8, 2017

Non-binary low density parity check code column rotation

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Quick Facts
Patent No.
US 9,727,419
App. No.
14/935,333
Granted
Aug 8, 2017
Kind
B2
Abstract

An apparatus for processing data includes a storage medium operable to store encoded data, and a read channel circuit with a low density parity check encoder operable to encode data to generate the encoded data, and a low density parity check decoder operable to decode the encoded data retrieved from the storage medium. The read channel circuit is operable to perform a column rotation on the encoded data prior to storage and after retrieval before decoding.

Claims (33)

1. An apparatus comprising:

a storage medium operable to store encoded data; and

a read channel circuit comprising a low density parity check encoder operable to encode data to generate the encoded data, and a low density parity check decoder operable to decode the encoded data retrieved from the storage medium, wherein the read channel circuit is operable to perform a column rotation on the encoded data prior to storage and after retrieval before decoding the encoded data, wherein the column rotation comprises reordering extrinsic log likelihood ratios according to a rotation vector.

2. The apparatus of claim 1 , wherein the low density parity check decoder comprises a non-binary decoder.

3. The apparatus of claim 1 , wherein the column rotation comprises multiplying each non-zero entry in a column of a low density parity check H matrix by a constant from a Galois Field.

4. The apparatus of claim 1 , wherein the read channel circuit comprises a data detector circuit configured to perform global detection and decoding iterations with the low density parity check decoder.

5. The apparatus of claim 4 , wherein the read channel circuit further comprises a first column rotation circuit configured to perform the column rotation on an output of the data detector circuit and a second column rotation circuit configured to perform the column rotation on an output of the low density parity check decoder.

6. The apparatus of claim 1 , wherein the read channel circuit comprises a column rotation circuit configured to perform the column rotation on an output of the low density parity check encoder.

7. The apparatus of claim 1 , wherein the low density parity check decoder comprises a column rotation circuit configured to perform the column rotation on an H matrix.

8. The apparatus of claim 1 , the read channel circuit further comprising a read only memory operable to contain at least one rotation vector.

9. The apparatus of claim 8 , wherein the at least one rotation vector comprises a plurality of rotation vectors, each comprising a Galois Field value for each column in an H matrix.

10. The apparatus of claim 1 , wherein the read channel circuit is operable to generate a rotation vector used for the column rotation based on a seed.

11. The apparatus of claim 1 , wherein the read channel circuit is operable to select from among a plurality of rotation vectors based at least in part on a channel bit density.

12. A method of encoding and decoding data, comprising:

encoding data according to a low density parity check matrix to yield encoded data;

performing a column rotation of the encoded data using a rotation vector to yield column-rotated encoded data;

performing a column rotation of the column-rotated encoded data to yield the encoded data;

decoding the encoded data according to the low density parity check matrix to yield the data;

retrieving the rotation vector from a read only memory from among a plurality of rotation vectors based at least in part on a channel bit density; and

optimizing the plurality of rotation vectors based on a trapping set list for the low density parity check matrix.

13. The method of claim 12 , further comprising storing the column-rotated encoded data on a storage medium.

14. The method of claim 12 , wherein the rotation vector comprises a Galois Field value for each circulant column in the low density parity check matrix.

15. The method of claim 12 , wherein the plurality of rotation vectors are optimized based on a symbol weight and a hamming weight of the trapping set list.

16. The method of claim 12 , further comprising generating the rotation vector based upon a seed value prior to the column rotations.

17. A storage system comprising:

a storage medium;

a low density parity check encoder operable to encode user data to be stored on the storage medium;

a read channel circuit operable to perform column rotations of encoded user data, wherein the column rotation comprises reordering extrinsic log likelihood ratios according to a rotation vector;

the read channel circuit further operable to perform column rotations of the encoded data after retrieval from the storage medium; and

a low density parity check decoder operable to decode the encoded user data from the storage medium.

18. The storage system of claim 17 , wherein the low density parity check decoder comprises a non-binary decoder.

19. The storage system of claim 17 , wherein the read channel circuit comprises a data detector circuit configured to perform global detection and decoding iterations with the low density parity check decoder.

20. The storage system of claim 19 , wherein the read channel circuit further comprises a first column rotation circuit configured to perform the column rotation on an output of the data detector circuit and a second column rotation circuit configured to perform the column rotation on an output of the low density parity check decoder.

Assignments (7)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2015
From: WU, XUEBIN; HAN, YANG; YANG, SHAOHUA
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036984/0064 →