Delay locked loop and associated control method

1. A delay locked loop, comprising:

a programmable delay line, receiving an input signal to generate a first internal signal and an output signal, the output signal and the first internal signal having different phases;

a control logic, receiving the output signal and accordingly providing a selection signal;

a selection circuit, coupled to the control logic, selectively providing a reference clock signal or the output signal as the input signal; and

a mask, coupled to the selection circuit, the control logic and the delay line, controlled by the first internal signal and the selection signal to determine whether to utilize the reference clock signal as the input signal.

2. The delay locked loop according to claim 1 , wherein the mask comprises a time controller, which generates a control signal according to the first internal signal and the selection signal.

3. The delay locked loop according to claim 2 , wherein the selection signal selectively provides the reference clock signal or the output signal as the input signal according to the control signal.

4. The delay locked loop according to claim 2 , wherein the mask further comprises a sub-circuit, which selectively provides the reference clock signal to the selection circuit.

5. The delay locked loop according to claim 1 , wherein when the selection circuit provides the output signal as the input signal, the delay line forms a ring oscillator, and a phase difference between the first internal signal and the output signal is substantially between 180 degrees and 360 degrees.

6. The delay locked loop according to claim 5 , wherein the phase difference is substantially between 270 degrees and 315 degrees.

7. The delay locked loop according to claim 1 , wherein the programmable delay line further generates a second internal signal; the first internal signal, the second internal signal and the output signal have different phases; and the mask determines whether to utilize the reference clock signal as the input signal according to the first internal signal, the second internal signal and the selection signal.

8. The delay locked loop according to claim 7 , wherein when the selection circuit selects the output signal as the input signal, the delay line forms a ring oscillator, and a first phase difference between the first internal signal and the input signal and a second phase difference between the second internal signal and the input signal are substantially between 270 degrees and 315 degrees.

9. The delay locked loop according to claim 1 , wherein the control logic provides the selection signal according to a falling edge of the output signal.

10. The delay locked loop according to claim 9 , wherein the control logic comprises a divider, which provides an indication signal according to the output signal to indicate a last clock period, and the selection signal is generated according to the falling edge and the indication signal.

11. The delay locked loop according to claim 10 , wherein the selection signal provides a pulse, which is triggered by the falling edge and ends at a next falling edge of the output signal.

12. A control method, applied to a delay locked loop, comprising:

delaying an input signal to generate an internal signal;

delaying the internal signal to generate an output signal; and

selectively providing a reference clock signal or the output signal as the input signal according to the output signal and the internal signal.

13. The method according to claim 12 , wherein the step of selectively utilizing the reference clock signal as the input signal comprises:

providing a selection signal according to the output signal to control a selection circuit to selectively provide the reference clock signal or the output signal as the input signal; and

generating a control signal according to the selection signal and the internal signal to selectively input the reference clock signal to the selection circuit.

14. The method according to claim 12 , wherein the step of selectively utilizing the reference clock signal as the input signal comprises:

providing a control signal according to the selection signal and the internal signal to control a selection circuit to selectively provide the reference clock signal or the output signal as the input signal.

15. The method according to claim 12 , wherein the internal signal is a first internal signal, the method further comprising:

delaying the first internal signal to generate a second internal signal; and

delaying the second internal signal to generate the output signal;

wherein, the reference clock signal is selectively utilized as the input signal according to the output signal, the first internal signal and the second internal signal.

16. The method according to claim 15 , wherein when the output signal is utilized as the input signal, a phase of the output signal is substantially 0 degree, and phases of the first and second internal signals are substantially between 180 degrees and 360 degrees.

17. The method according to claim 16 , further comprising:

selectively utilizing the reference clock signal as the input signal according to an OR operation result of the first and second internal signals.

18. The method according to claim 12 , wherein the step of selectively utilizing the reference clock signal as the input signal comprises:

performing an integer division on the output signal to generate an indication signal to indicate a beginning and an end of a last period of the output signal.

19. The method according to claim 18 , further comprising:

generating a selection signal according to the indication signal and the output signal, the selection signal providing a pulse that begins at a falling edge of the output signal and ends at a next falling edge of the output signal.

20. The method according to claim 19 , further comprising:

providing a control signal according to the selection signal and the internal signal to selectively utilize the reference clock signal as the input signal.