IP Library Granted Patent US 10,116,952
Granted Patent B2
US 10,116,952 · App. 14/992,384 · Granted Oct 30, 2018

Bitstream decoding method and bitstream decoding circuit

Inventors: He-Yuan Lin (Zhubei, TW); Ya-Ting Yang (Zhubei, TW); Yi-Shin Tung (Zhubei, TW)
Assignee: MSTAR SEMICONDUCTOR, INC.
H04N19/44H04L65/607H04N19/132H04N19/156H04N19/172
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Quick Facts
Patent No.
US 10,116,952
App. No.
14/992,384
Granted
Oct 30, 2018
Kind
B2
Abstract

A stream decoding method is provided. The stream includes a plurality of frames. The method includes: obtaining a display order of a current frame that belongs to a group by parsing a header of the current frame; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame.

Claims (42)

1. A method for decoding a bitstream, the bitstream comprising a plurality of frames, the method comprising:

receiving the bitstream at a decoding circuit, which performs steps of:

obtaining a display order of a current frame in the bitstream by parsing a header of the current frame, the current frame belonging to a group; and

determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame,

wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame comprises:

determining whether the display order of the current frame is later than display orders of previous frames in the group according to the display order of the current frame, and

decoding the current frame according to a determination result indicating that the display order of the current frame is later than the display orders of all the previous frames in the group thereby ensuring that at least all P-frames of the group are decoded and not dropped.

2. The method according to claim 1 , further comprising:

obtaining one or multiple reference frames of the current frame by parsing the header of the current frame in the bitstream; and

determining whether to decode the current frame or to drop instead of decoding the current frame according to the one or multiple reference frames of the current frame.

3. The method according to claim 2 , wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the one or multiple reference frames of the current frame comprises:

determining whether the current frame jointly refers to the frame having previous and adjacent display orders and the frame having a next display order in the group according to the one or multiple reference frames.

4. The method according to claim 3 , further comprising:

dropping instead of decoding the current frame according to a determination result indicating that the current frame jointly refers to the frame having the previous and adjacent display orders and the frame having the next display order in the group.

5. The method according to claim 1 , wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame according the display order of the current frame comprises:

determining whether the display order of the current frame is an integral multiple of a value according to the display order of the current frame.

6. The method according to claim 5 , further comprising:

decoding the current frame according to a determination result indicating that the display order of the current frame is an integral multiple of the value.

7. The method according to claim 5 , further comprising:

dropping instead of decoding the current frame according to a determination result indicating that the display order of the current frame is not an integral multiple of the value.

8. A bitstream decoding circuit, comprising:

a decoder, accessing a bitstream comprising a plurality of frames; and

a control unit, coupled to the decoder, performing steps of:

obtaining a display order of a current frame in the bitstream by parsing a header of the current frame, the current frame belonging to a group; and

determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame,

wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame comprises:

determining whether the display order of the current frame is later than display orders of previous frames in the group according to the display order of the current frame

wherein the control unit further performs a step of:

controlling the decoder to decode the current frame according to a determination result indicating that the display order of the current frame is later than the display orders of all the previous frames in the group thereby ensuring that at least all P-frames of the group are decoded and not dropped.

9. The bitstream decoding circuit according to claim 8 , wherein the control unit further performs a step of:

obtaining one or multiple reference frames of the current frame by parsing the header of the current frame in the bitstream; and

determining whether to decode the current frame or to drop instead of decoding the current frame according to the one or multiple reference frames of the current frame.

10. The bitstream decoding circuit according to claim 9 , wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the one or multiple reference frames of the current frame comprises:

determining whether the current frame jointly refers to the frame having previous and adjacent display orders and the frame having a next display order in the group according to the one or multiple reference frames.

11. The bitstream decoding circuit according to claim 10 , wherein the control unit further performs a step of:

dropping instead of decoding the current frame according to a determination result indicating that the current frame jointly refers to the frame having the previous and adjacent display orders and the frame having the next display order in the group.

12. The bitstream decoding circuit according to claim 8 , wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame according the display order of the current frame comprises:

determining whether the display order of the current frame is an integral multiple of a value according to the display order of the current frame.

13. The bitstream decoding circuit according to claim 12 , wherein the control unit further performs a step of:

decoding the current frame according to a determination result indicating that the display order the current frame is an integral multiple of the value.

14. The bitstream decoding circuit according to claim 12 , wherein the control unit further performs a step of:

dropping instead of decoding the current frame according to a determination result indicating that the display order of the current frame is not an integral multiple of the value.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2021
From: MEDIATEK INC.
To: XUESHAN TECHNOLOGIES INC.
Reel/Frame 056593/0167 →
MERGER Recorded Oct 8, 2019
From: MSTAR SEMICONDUCTOR, INC.
To: MEDIATEK INC.
Reel/Frame 050665/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2016
From: LIN, HE-YUAN; YANG, YA-TING; TUNG, YI-SHIN
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 037459/0761 →
Priority Claims (1)
TW 104139947 A · Nov 30, 2015 · national
Continuity (1)
Related Publication 20170155918A1 · Jun 1, 2017
Cited By (2)
US 12,335,500 US 12,413,769