Near field RF communicator and timing apparatus
A near field communications (NFC) device is disclosed that detects an envelope of a radio frequency (RF) signal. The NFC device includes a peak detector that determines the envelope of the RF signal. The peak detector compares a first differential signal voltage to a second differential signal voltage. The peak detector delays a rising edge of a first differential signal and provides the first differential signal voltage to the peak detector output when the first differential signal voltage is greater than the second differential signal voltage. The peak detector delays a falling edge of a second differential signal and provides the second differential signal voltage to the peak detector output when the second differential signal voltage is greater than the first differential signal voltage.
1. A peak detector for a near field communications (NFC) device, the peak detector comprising:
a delay line configured to delay a clock signal to provide a delayed clock signal;
a phase comparer configured to provide a control signal to the delay line based on a comparison of the clock signal and the delayed clock signal, the control signal being configured to adjust a delay of the delay line based on a voltage level change of the clock signal;
an edge detector configured to detect an edge of the clock signal as the clock signal propagates through the delay line; and
a logic element configured to sample an output of the edge detector when the output of the delay line indicates an edge of the delayed clock signal.
2. The peak detector of claim 1 , wherein the edge of the delayed clock signal comprises a rising edge.
3. The peak detector of claim 2 , wherein an output of the edge detector indicates that the delay of the delay line is longer than a clock period of the clock signal.
4. The peak detector of claim 2 , wherein an output of the edge detector indicates that the delay of the delay line is shorter than or equal to a clock period of the clock signal.
5. The peak detector of claim 1 , wherein the phase comparer is further configured to control the plurality of delay elements to configure each delay element to delay the clock signal for an equal period.
6. A peak detector for a near field communications (NFC) device, the peak detector comprising:
a delay line configured to delay a clock signal to provide a delayed clock signal; and
a phase comparer configured to provide a control signal to the delay line based on a comparison of the clock signal and the delayed clock signal, the control signal being configured to adjust a delay of the delay line based on a voltage level change of the clock signal;
an auxiliary delay line configured to provide an auxiliary delay; and
a logic circuit configured to provide a reset signal to the phase comparer when a total delay by the delay line and the auxiliary delay is greater than one clock cycle.
7. The peak detector of claim 6 , further comprising:
an edge detector configured to detect a rising edge of the clock signal as the clock signal propagates through the delay line; and
a logic element configured to sample an output of the edge detector based on the delayed clock signal.
8. The peak detector of claim 7 , wherein the logic element is configured to sample the edge detector when the output of the delay line indicates a rising edge.
9. The peak detector of claim 8 , wherein an output of the edge detector indicates that the delay of the delay line is longer than a clock period of the clock signal.
10. The peak detector of claim 8 , wherein an output of the edge detector indicates that the delay of the delay line is shorter than or equal to a clock period of the clock signal.
11. The peak detector of claim 7 , wherein the phase comparer is further configured to control the plurality of delay elements to configure each delay element to delay the clock signal for an equal period.
12. A peak detector for a near field communications (NFC) device, the peak detector comprising:
a delay line configured to delay a clock signal to provide a delayed clock signal;
a phase comparer configured to provide a control signal to the delay line based on a comparison of the clock signal and the delayed clock signal, the control signal being configured to adjust a delay of the delay line based on a voltage level change of the clock signal;
an edge detector configured to detect a rising edge of the clock signal as the clock signal propagates through the delay line; and
a logic element configured to sample an output of the edge detector based on the delayed clock signal.
13. The peak detector of claim 12 , wherein the logic element is configured to sample the edge detector when the output of the delay line indicates a rising edge.
14. The peak detector of claim 13 , wherein an output of the edge detector indicates that the delay of the delay line is longer than a clock period of the clock signal.
15. The peak detector of claim 13 , wherein an output of the edge detector indicates that the delay of the delay line is shorter than or equal to a clock period of the clock signal.
16. The peak detector of claim 12 , wherein the phase comparer is further configured to control the plurality of delay elements to configure each delay element to delay the clock signal for an equal period.