Semiconductor device and a manufacturing method thereof
View Patent ↗A semiconductor device has a chip region including a back-side illumination type photoelectric conversion element, a mark-like appearance part, a pad electrode, and a coupling part. The mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in a semiconductor substrate. The pad electrode is arranged at a position overlapping the mark-like appearance part. The coupling part couples the pad electrode and mark-like appearance part. At least a part of the pad electrode on the other main surface side of the substrate is exposed through an opening reaching the pad electrode from the other main surface side of the substrate. The mark-like appearance part and coupling part are arranged to at least partially surround the outer circumference of the opening in plan view.
1. A semiconductor device comprising:
a chip region,
the chip region including:
a semiconductor substrate having a first surface;
a photoelectric conversion element formed on the first surface;
a pad electrode;
a seal ring connected to the pad electrode; and
a film in a first trench formed in the semiconductor substrate and connected to the seal ring,
wherein at least a part of the pad electrode on the side facing the first surface is connected to a second trench having two openings in the semiconductor substrate, and
wherein the seal ring comprises two metal layers and surrounds the second trench.
2. The semiconductor device according to claim 1 ,
wherein the thickness of either one of the two metal layer is same as one of first-layer metal wire electrically connected to an impurity region via single contact conductive layer.
3. The semiconductor device according to claim 2 ,
wherein the first trench has two openings in the semiconductor substrate.
4. The semiconductor device according to claim 2 ,
wherein the film in the first trench is at least a part of alignment mark structure.
5. The semiconductor device according to claim 4 ,
wherein the alignment structure comprises a conductive film over the film.
6. The semiconductor device according to claim 4 ,
wherein the alignment structure comprises a conductive film and an antireflection film.
7. The semiconductor device according to claim 4 , further comprising a second alignment structure comprising a third trench having an opening on the first surface side of the semiconductor substrate and disposed in dicing line region.
8. A semiconductor device comprising:
a chip region,
the chip region including:
a semiconductor substrate having a first surfaces;
a photoelectric conversion element formed on the first surface;
a pad electrode;
a seal ring connected to the pad electrode; and
a film in a first trench formed in the semiconductor substrate and connected to the seal ring,
wherein at least a part of the pad electrode on the side facing the first surface is connected to a second trench having two openings in the semiconductor substrate,
wherein the seal ring comprises two metal layers and surrounds the second trench, and
wherein the pad electrode comprises two metal layers and the contact area of them is smaller than the larger one of the metal layers.
9. The semiconductor device according to claim 8 ,
wherein the thickness of either one of the two metal layer is same as one of first-layer metal wire electrically connected to an impurity region via single contact conductive layer.
10. The semiconductor device according to claim 9 ,
wherein the first trench has two openings in the semiconductor substrate.
11. The semiconductor device according to claim 9 ,
wherein the film in the first trench is at least a part of alignment mark structure.
12. The semiconductor device according to claim 11 ,
wherein the alignment structure comprises a conductive film over the film.
13. The semiconductor device according to claim 11 ,
wherein the alignment structure comprises a conductive film and an antireflection film.
14. The semiconductor device according to claim 11 , further comprising a second alignment structure comprising a third trench having an opening on the first surface side of the semiconductor substrate and disposed in dicing line region.
15. A semiconductor device comprising:
a chip region,
the chip region including:
a semiconductor substrate having a first surfaces;
a photoelectric conversion element formed on the first surface;
a metal plate;
a seal ring connected to the metal plate; and
a film in a first trench formed in the semiconductor substrate and connected to the seal ring,
wherein at least a part of the metal plate on the side facing the first surface is connected to a second trench having two openings in the semiconductor substrate, and
wherein the seal ring comprises two metal layers and surrounds the second trench and the chip region.
16. The semiconductor device according to claim 15 ,
wherein the thickness of either one of the two metal layer is same as one of first-layer metal wire electrically connected to an impurity region via single contact conductive layer.
17. The semiconductor device according to claim 16 ,
wherein the first trench has two openings in the semiconductor substrate.
18. The semiconductor device according to claim 16 ,
wherein the film in the first trench is at least a part of alignment mark structure.
19. The semiconductor device according to claim 18 ,
wherein the alignment structure comprises a conductive film over the film.
20. The semiconductor device according to claim 18 ,
wherein the alignment structure comprises a conductive film and an antireflection film.