Semiconductor device

1. A semiconductor device comprising:

a semiconductor chip; and

a control chip configured to control said semiconductor chip,

wherein said semiconductor device comprises:

a first semiconductor layer in which a first conductive type impurity is heavily doped;

a second semiconductor layer in which the first conductive type impurity is lightly doped and which is joined onto said first semiconductor layer;

a first power transistor having a channel of the first conductive type and formed in a surface region of said second semiconductor layer;

a transistor formed in a surface region of said second semiconductor layer; and

a first diffusion layer region of a second conductive type formed in a surface region of said second semiconductor layer to separate said first power transistor from said transistor,

wherein said first semiconductor layer functions as a drain of said first power transistor, and

wherein said first diffusion layer region is set to the same voltage as that of said drain.

2. The semiconductor device according to claim 1 , wherein the first conductive type is an N-type, and the second conductive type is a P-type, and

wherein said first diffusion layer region is set to a relatively high power supply voltage.

3. The semiconductor device according to claim 1 , wherein said transistor is a second power transistor having the first conductive type channel and formed in a surface region of said second semiconductor layer and said first semiconductor layer functions as the drain of said second power transistor.

4. The semiconductor device according to claim 1 , wherein said transistor is at least one of a planar-type of transistor having the first conductive type channel and a planar-type transistor having a second conductive type channel, which are formed in a surface region of the second semiconductor layer.

5. The semiconductor device according to claim 1 , further comprising:

an electrode layer connected with said first diffusion layer region and extending along said first diffusion layer region; and

a second diffusion layer region of the first conductive type formed in a surface region of said second semiconductor layer and connected with an interconnection layer.

6. The semiconductor device according to claim 1 , further comprising:

an electrode layer connected with said first diffusion layer region and extending along said first diffusion layer region; and

a second diffusion layer region of the first conductive type formed in a surface region of said second semiconductor layer along a side of said first diffusion layer region which is opposite to said first power transistor, to be connected with said electrode layer.

7. The semiconductor device according to claim 3 , further comprising:

a plurality of power transistors which include said first power transistor and said second power transistor,

wherein said first semiconductor layer functions as drains of said plurality of power transistors, and

wherein said first diffusion layer region is formed to provide a boundary between sources of adjacent two power transistors of said plurality of power transistors.

8. The semiconductor device according to claim 1 , wherein said first power transistor comprises a base diffusion layer of the second conductive type functioning as a channel, and

wherein a diffusion depth of said first diffusion layer region is substantially the same as the diffusion depth of said base diffusion layer.

9. The semiconductor device according to claim 1 , wherein said first power transistor comprises:

a base diffusion layer of a second conductive type functioning a channel; and

a well diffusion layer provided to surround said base diffusion layer, and

wherein a diffusion depth of said first diffusion layer region is substantially the same as the diffusion depth of said well diffusion layer.

10. The semiconductor device according to claim 1 , wherein said first power transistor comprises:

a base diffusion layer of a second conductive type functioning a channel;

a gate formed to pass through said base diffusion layer from a surface side to an internal side; and

a source of the first conductive type formed on a side of said gate in a surface region of said base diffusion layer.

11. An intelligent power device comprising:

a semiconductor chip to be coupled to a load; and

a control chip configured to control said semiconductor chip,

wherein said semiconductor chip comprises:

a first semiconductor layer in which a first conductive type impurity is heavily doped;

a second semiconductor layer in which the first conductive type impurity is lightly doped and which is joined onto said first semiconductor layer;

a first power transistor having a channel of the first conductive type and formed in a surface region of said second semiconductor layer;

a transistor formed in a surface region of said second semiconductor layer; and

a first diffusion layer region of a second conductive type formed in a surface region of said second semiconductor layer to separate said first power transistor from said transistor,

wherein said first semiconductor layer functions as a drain of said first power transistor, and

wherein said first diffusion layer region is set to the same voltage as that of said drain.

12. The intelligent power device according to claim 11 , wherein said load includes a lamp.

13. An intelligent power device comprising:

a semiconductor chip; and

a motor coupled to said semiconductor chip,

wherein said semiconductor chip comprises:

a first semiconductor layer in which a first conductive type impurity is heavily doped;

a second semiconductor layer in which the first conductive type impurity is lightly doped and which is joined onto said first semiconductor layer;

a first power transistor having a channel of the first conductive type and formed in a surface region of said second semiconductor layer;

a transistor formed in a surface region of said second semiconductor layer; and

a first diffusion layer region of a second conductive type formed in a surface region of said second semiconductor layer to separate said first power transistor from said transistor,

wherein said first semiconductor layer functions as a drain of said first power transistor, and

wherein said first diffusion layer region is set to the same voltage as that of said drain.

14. The intelligent power device according to claim 13 , wherein said transistor is a second power transistor having the first conductive type channel and formed in a surface region of said second semiconductor layer and said first semiconductor layer functions as the drain of said second power transistor.

15. The intelligent power device according to claim 14 , wherein one end of said motor is coupled to said first power transistor and another end of said motor is coupled to said second power transistor.

16. The intelligent power device according to claim 13 , further comprising:

a controller configured to control said semiconductor chip.