Internal clock signal control for display device, display driver and display device system

1. A display device, comprising:

a display panel; and

a display driver driving the display panel,

wherein the display driver is connected to a host with a clock lane and at least one data lane,

wherein the display driver comprises:

an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal;

a control circuit configured to output an internal clock signal synchronous with the external clock signal; and

drive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal outputted by the control circuit,

wherein, when the clock lane and the data lane are set to a first mode, the interface circuit is configured to perform a clock recovery on the data signal transmitted over the data lane and generate the reception data by sampling the data signal in synchronization with a recovered clock signal obtained by the clock recovery,

wherein, when the clock lane and the data lane are set to a second mode, the interface circuit is configured to generate the reception data by sampling the data signal in synchronization with the external clock signal transmitted over the clock lane, and

wherein the control circuit is configured to output the internal clock signal in response to a type of a reception packet included in the reception data when the clock lane and the data lane are set to the second mode.

2. The display device according to claim 1 , wherein the control circuit comprises a pixel counter, and

wherein the control circuit is configured to, when detecting a first packet in the reception data, start outputting the internal clock signal, start counting using the pixel counter, and stop the output of the internal clock signal in response to a count value of the pixel counter reaching a predetermined value, the first packet indicating a start of transmitting the image data from the host to the display driver.

3. The display device according to claim 1 , wherein the control circuit is configured to, when detecting a reception packet of a specific type in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration.

4. The display device according to claim 1 , wherein the control circuit is configured to, when detecting a second packet in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration, the second packet indicating a start of a horizontal sync period.

5. The display device according to claim 1 , wherein the control circuit is configured to, when detecting a third packet in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration, the third packet incorporating a command.

6. The display device according to claim 1 , wherein the mobile industry processor interface-display serial interface (MIPI-DSI) is used to communicate between the display driver and the host,

wherein the first mode is the low power (LP) mode, and

wherein the second mode is the high speed (HP) mode.

7. A display driver to be connected to a host with a clock lane and at least one data lane to drive a display panel, the driver comprising:

an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal;

a control circuit configured to output an internal clock signal synchronous with the external clock signal; and

a drive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal outputted by the control circuit,

wherein, when the clock lane and the data lane are set to a first mode, the interface circuit is configured to perform a clock recovery on the data signal transmitted over the data lane, and generate the reception data by sampling the data signal in synchronization with a recovered clock signal obtained by the clock recovery,

wherein, when the clock lane and the data lane are set to a second mode, the interface circuit is configured to generate the reception data by sampling the data signal in synchronization with the external clock signal transmitted over the clock lane, and

wherein the control circuit is configured to output the internal clock signal in response to a type of a reception packet included in the reception data, when the when the clock lane and the data lane are set to the second mode.

8. The display driver according to claim 7 , wherein the control circuit comprises a pixel counter, and

wherein the control circuit is configured to, when detecting a first packet in the reception data, start outputting the internal clock signal, start counting using the pixel counter, and stop the output of the internal clock signal in response to a count value of the pixel counter reaching a predetermined value, the first packet indicating a start of transmitting the image data from the host to the display driver.

9. The display driver according to claim 7 , wherein the control circuit is configured to, when detecting a reception packet of a specific type in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration.

10. The display driver according to claim 7 , wherein the control circuit is configured to, when detecting a second packet in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration, the second packet indicating a start of a horizontal sync period.

11. The display driver according to claim 7 , wherein the control circuit is configured to, when detecting a third packet in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration, the third packet incorporating a command.

12. The display driver according to claim 7 , wherein the mobile industry processor interface-display serial interface (MIPI-DSI) is used to communicate between the display driver and the host,

wherein the first mode is the low power (LP) mode, and

wherein the second mode is the high speed (HP) mode.

13. A display device system, comprising:

a host; and

a display device including:

a display panel; and

a display driver driving the display panel,

wherein the display driver and the host are connected to each other with a clock lane and at least one a data lane,

wherein the display driver comprises:

an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal;

a control circuit configured to output an internal clock signal synchronous with the external clock signal; and

a drive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal outputted by the control circuit,

wherein, when the clock lane and the data lane are set to a first mode, the interface circuit is configured to perform a clock recovery on the data signal transmitted over the data lane, and generate the reception data by sampling the data signal in synchronization with a recovered clock signal obtained by the clock recovery,

wherein, when the clock lane and the data lane are set to a second mode, the interface circuit is configured to generate the reception data by sampling the data signal in synchronization with the external clock signal transmitted over the clock lane, and

wherein the control circuit is configured to output the internal clock signal in response to a type of a reception packet included in the reception data, when the when the clock lane and the data lane are set to the second mode.

14. The display device system according to claim 13 , wherein the clock lane and the data lane are set to the second mode during the entirety of each horizontal sync period.

15. The display device system according to claim 13 , wherein the mobile industry processor interface-display serial interface (MIPI-DSI) is used to communicate between the display driver and the host,

wherein the first mode is the low power (LP) mode, and

wherein the second mode is the high speed (HP) mode.

16. The display device system according to claim 13 , wherein the control circuit is configured to, when detecting a reception packet of a specific type in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration.

17. The display device system according to claim 13 , wherein the control circuit comprises a pixel counter, and

wherein the control circuit is configured to, when detecting a first packet in the reception data, start outputting the internal clock signal, start counting using the pixel counter, and stop the output of the internal clock signal in response to a count value of the pixel counter reaching a predetermined value, the first packet indicating a start of transmitting the image data from the host to the display driver.

18. The display device system according to claim 13 , wherein the control circuit is configured to, when detecting a second packet in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration, the second packet indicating a start of a horizontal sync period.

19. The display device system according to claim 13 , wherein the control circuit is configured to, when detecting a third packet in the reception data received from the interface circuit, output the internal clock signal to the drive circuitry for a given time duration, the third packet incorporating a command.

20. The display device system according to claim 13 , wherein the control circuit is configured to output the internal clock signal to the drive circuitry when detecting at least one of a horizontal sync packet, a command packet, and a packed packet stream.