IP Library Patent Application 15084765
Patent Application
App. No. 15/084,765

COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

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Quick Facts
Patent No.
US None
App. No.
15/084,765
Abstract

A compound semiconductor device includes: a substrate; a nucleation layer over the substrate; a first buffer layer over the nucleation layer; a second buffer layer between the nucleation layer and the first buffer layer, the second buffer layer containing an acceptor impurity element or a donor impurity element at a higher concentration than the first buffer layer; a carrier transit layer in contact with the first buffer layer; a carrier supply layer over the carrier transit layer; and a gate electrode, a source electrode, and a drain electrode above the carrier supply layer.

Claims (39)

1 . A compound semiconductor device comprising:

a substrate;

a nucleation layer over the substrate;

a first buffer layer over the nucleation layer;

a second buffer layer between the nucleation layer and the first buffer layer, the second buffer layer containing an acceptor impurity element or a donor impurity element at a higher concentration than the first buffer layer;

a carrier transit layer in contact with the first buffer layer;

a carrier supply layer over the carrier transit layer; and

a gate electrode, a source electrode, and a drain electrode above the carrier supply layer.

2 . The compound semiconductor device according to claim 1 , wherein a lower surface of the second buffer layer is in contact with an upper surface of the nucleation layer.

3 . The compound semiconductor device according to claim 1 , wherein the acceptor impurity element is Mg or Zn or combination thereof.

4 . The compound semiconductor device according to claim 1 , wherein the donor impurity element is Si, O, Ge, Te, or Se or any combination thereof.

5 . The compound semiconductor device according to claim 1 , wherein a concentration of the acceptor impurity element or the donor impurity element in the second buffer layer is 1×10 18 cm −3 or more and 1×10 21 cm −3 or less.

6 . The compound semiconductor device according to claim 1 , wherein the substrate is a Si substrate, a SiC substrate, a sapphire substrate, a Ga 2 O 3 substrate, or an AlN substrate.

7 . The compound semiconductor device according to claim 1 , wherein the nucleation layer is not intentionally doped with impurity.

8 . The compound semiconductor device according to claim 1 , wherein the second buffer layer is composed of a single layer.

9 . A power supply apparatus, comprising a compound semiconductor device, wherein the compound semiconductor device comprises:

a substrate;

a nucleation layer over the substrate;

a first buffer layer over the nucleation layer;

a second buffer layer between the nucleation layer and the first buffer layer, the second buffer layer containing an acceptor impurity element or a donor impurity element at a higher concentration than the first buffer layer;

a carrier transit layer in contact with the first buffer layer;

a carrier supply layer over the carrier transit layer; and

a gate electrode, a source electrode, and a drain electrode above the carrier supply layer.

10 . An amplifier, comprising a compound semiconductor device, wherein the compound semiconductor device comprises:

a substrate;

a nucleation layer over the substrate;

a first buffer layer over the nucleation layer;

a second buffer layer between the nucleation layer and the first buffer layer, the second buffer layer containing an acceptor impurity element or a donor impurity element at a higher concentration than the first buffer layer;

a carrier transit layer in contact with the first buffer layer;

a carrier supply layer over the carrier transit layer; and

a gate electrode, a source electrode, and a drain electrode above the carrier supply layer.

11 . A method of manufacturing a compound semiconductor device comprising:

forming a nucleation layer over a substrate;

forming a first buffer layer over the nucleation layer;

forming a second buffer layer between the nucleation layer and the first buffer layer, the second buffer layer containing an acceptor impurity element or a donor impurity element at a higher concentration than the first buffer layer;

forming a carrier transit layer in contact with the first buffer layer;

forming a carrier supply layer over the carrier transit layer; and

forming a gate electrode, a source electrode, and a drain electrode above the carrier supply layer.

12 . The method according to claim 11 , wherein a lower surface of the second buffer layer is in contact with an upper surface of the nucleation layer.

Assignments (2)
SECURITY INTEREST Recorded Oct 27, 2017
From: SI-BONE, INC.
To: BIOPHARMA CREDIT INVESTMENTS IV SUB LP
Reel/Frame 043975/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: NISHIMORI, MASATO; IMADA, TADAHIRO; ZHU, LEI
To: FUJITSU LIMITED
Reel/Frame 038138/0749 →