IP Library Patent Application 15086720
Patent Application
App. No. 15/086,720

CAPACITANCE SENSOR WITH SENSOR CAPACITANCE COMPENSATION

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Quick Facts
Patent No.
US None
App. No.
15/086,720
Abstract

A capacitance sensing circuit may include a switching circuit configured to generate a sensor current by charging and discharging a capacitive sensor electrode, and a current mirror that generates a mirror current based on the sensor current. Based on the mirror current, a measurement circuit generates an output signal representative of a capacitance of the capacitive sensor electrode.

Claims (41)

1 . An integrated circuit (IC) comprising:

a terminal configured to be coupled to a capacitive sensor element;

a switching circuit coupled between the terminal and a compensation circuit;

a current mirror having an input coupled to the switching circuit and the compensation circuit, and an output coupled to a first input of a comparator; and

wherein the switching circuit is configured to couple the terminal to a first supply voltage in a first state and to the compensation circuit and the current mirror in a second state.

2 . The IC of claim 1 , wherein the compensation circuit is coupled between the switching circuit and a second power supply voltage.

3 . The IC of claim 1 , wherein the first supply voltage is a ground voltage.

4 . The IC of claim 2 , wherein the second supply voltage is a positive voltage.

5 . The IC of claim 2 , wherein the first supply voltage is a positive voltage and the second supply voltage is a ground voltage.

6 . The IC of claim 1 , further comprising a timer circuit coupled to the output of the comparator and clocked by an oscillator.

7 . The IC of claim 1 , wherein the capacitance of the capacitive sensor element is affected by the proximity of a conductive object.

8 . The IC of claim 1 , further comprising a processing core coupled to the comparator and a communication block coupled to the processing core, wherein the communication block is configured to communicate with a host processor.

9 . The IC of claim 1 , wherein the compensation circuit comprises a current digital-to-analog-converter.

10 . A method comprising:

providing a terminal configured to be coupled to a capacitive sensor element;

providing a compensation circuit;

providing a switching circuit coupled between the terminal and the compensation circuit;

providing a current mirror having an input coupled to the switching circuit and to the compensation circuit;

providing a comparator having a first input coupled to the output of the current mirror;

configuring the terminal to be coupled to a first supply voltage using the switching circuit in a first state; and

configuring the terminal to be coupled to the compensation circuit and current mirror using the switching circuit in a second state.

11 . The method of claim 10 , further comprising configuring the compensation circuit to be coupled to a second power supply voltage.

12 . The method of claim 10 , wherein the first supply voltage is a ground voltage,

13 . The method of claim 11 , wherein the second supply voltage is a positive voltage.

14 . The method of claim 11 , wherein the first supply voltage is a positive voltage and the second supply voltage is a ground voltage.

15 . The method of claim 10 , wherein the capacitance of the capacitive sensor element is affected by the proximity of a conductive object.

16 . The method of claim 10 , further comprising:

providing a processing core coupled to the comparator;

providing a communication block coupled to the processing core; and

configuring the communication block to communicate with a host processor.

17 . A system comprising:

a capacitive sensor element;

a switching circuit coupled between the capacitive sensor element and a compensation circuit;

a current mirror having an input coupled to the switching circuit and the compensation circuit, and an output coupled to a first input of a comparator;

a processing core coupled to an output of the comparator;

a communication block coupled to the processing core; and

a host processor coupled to the communication block,

wherein the switching circuit is configured to couple the input terminal to a first supply voltage in a first state and to the compensation circuit and current mirror in a second state, and wherein the compensation circuit is coupled between the switching circuit and a second power supply voltage.

18 . The system of claim 17 , wherein the first supply voltage is a ground voltage and the second supply voltage is a positive voltage.

19 . The system of claim 17 , wherein the second supply voltage is a ground voltage and the first supply voltage is a positive voltage.

20 . The system of claim 17 , wherein the compensation circuit comprises a current digital-to-analog-converter.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040028/0054 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2016
From: MAHARYTA, ANDRIY; RYSHTUN, ANDRIY
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 039398/0650 →