IP Library Granted Patent US 10,223,322
Granted Patent B2
US 10,223,322 · App. 15/132,147 · Granted Mar 5, 2019

Systems and methods for channel information exchange in a PCIe environment

Inventors: Mohammad Mobin (Orefield, PA); Anup Tirumala (San Jose, CA); Haitao Xia (San Jose, CA)
Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
G06F13/4282G06F13/12
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Quick Facts
Patent No.
US 10,223,322
App. No.
15/132,147
Granted
Mar 5, 2019
Kind
B2
Abstract

Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing non-standard bus information.

Claims (53)

1. A data processing system, the system comprising:

a target device, wherein the target device includes:

a standard communication circuit; and

a side channel communication system including:

a first side channel communication circuit;

a second side channel communication circuit, wherein all of the standard communication circuit, the first side channel communication circuit, and the second side channel communication circuit communicate via a common bus but by different communication mechanisms; and

a side channel selector circuit operable to select one of the first side channel communication circuit or the second side channel communication circuit to perform side channel communications for the target device,

wherein selecting one of the first side channel communication circuit or the second side channel communication circuit is based at least in part on a determination that a mechanism and a location corresponding to the selected one of the first side channel communication circuit or the second side channel communication circuit is not utilized, and

wherein the determination that the mechanism and the location corresponding to the selected one of the first side channel communication circuit or the second side channel communication circuit is not utilized is made by a circuit in the target device.

2. The system of claim 1 , wherein the common bus is a PCie™ bus, and wherein the first side channel communication circuit is selected from a group consisting of: a circuit operable to communicate via a PCie™ configuration space, a circuit operable to communicate via a PCie™ extended capability structure, and a circuit operable to communicate via a PCie™ stack.

3. The system of claim 1 , the system further comprising:

a master device operable to communicate with the target device via the common bus.

4. The system of claim 1 , wherein the standard communication circuit provides access to a public location within the target device, and wherein the side channel communication system provides access to a non-public location within the target device.

5. The system of claim 4 , the system further comprising:

a master device operable to communicate with the target device via the common bus, wherein the master device accesses the public location directly using a mechanism implemented in the master device, and wherein the master device accesses the non-public location indirectly using a third party mechanism operating on the master device.

6. The system of claim 1 , wherein the first side channel communication circuit is a circuit operable to communicate via a PCie™ extended capability structure.

7. The system of claim 6 , wherein the standard communication circuit is operable to communicate via the common bus using a mechanism other than the PCie™ extended capability structure.

8. The system of claim 1 , wherein the target device is a storage device.

9. A data processing system, the system comprising:

a target device, wherein the target device includes:

a standard communication circuit; and

a side channel communication system including:

a first side channel communication circuit;

a second side channel communication circuit, wherein all of the standard communication circuit, the first side channel communication circuit, and the second side channel communication circuit communicate via a common bus but by different communication mechanisms; and

a side channel selector circuit operable to select one of the first side channel communication circuit or the second side channel communication circuit to perform side channel communications for the target device; and

a master device operable to communicate with the target device via the common bus;

wherein selecting one of the first side channel communication circuit or the second side channel communication circuit is based at least in part on a determination that a mechanism and a location corresponding to the selected one of the first side channel communication circuit or the second side channel communication circuit is not utilized, and

wherein the determination that the mechanism and the location corresponding to the selected one of the first side channel communication circuit or the second side channel communication circuit is not utilized is provided to the target device from the master device via the standard communication circuit.

10. A method for side channel communications, the method comprising:

providing a target device, the target device including:

a standard communication circuit operable to communicate via a PCie™ bus; and

a side channel communication circuit operable to communicate via a PCie™ extended capability structure at a defined location, wherein the standard communication circuit is operable to communicate via the PCie™ bus using a mechanism other than the PCie™ extended capability structure; and

selecting the defined location.

11. The method of claim 10 , wherein selecting the defined location comprises:

receiving the defined location via the standard communication circuit.

12. The method of claim 10 , wherein selecting the defined location comprises:

identifying by the target device a location in the PCie™ extended capability structure which is not used.

13. The method of claim 10 , the method further comprising:

using the standard communication circuit to communicate data from a public location within the target device; and

using the side channel communication circuit to communicate data from a non-public location within the target device.

14. A data processing system, the system comprising:

a target device, wherein the target device includes:

a standard communication circuit operable to communicate via a PCie™ bus;

a side channel communication circuit operable to communicate via a PCie™ extended capability structure at a defined location, wherein the standard communication circuit is operable to communicate via the PCie™ bus using a mechanism other than the PCie™ extended capability structure; and

a side channel selector circuit operable to select the defined location.

15. The system of claim 14 , the system further comprising:

a master device operable to communicate with the target device via the PCie™ bus.

16. The system of claim 14 , wherein the standard communication circuit provides access to a public location within the target device, and wherein the side channel communication circuit provides access to a non-public location within the target device.

17. The system of claim 14 , the system further comprising:

a master device operable to communicate with the target device via the PCie™ bus, wherein the master device accesses a public location within the target device directly using a mechanism implemented in the master device, and wherein the master device accesses a non-public location within the target device indirectly using a third party mechanism operating on the master device.

18. The system of claim 14 , wherein selecting the defined location is based at least in part on a determination that a location corresponding to the PCie™ extended capability structure is not utilized.

19. The system of claim 18 , wherein the determination that the location corresponding to the PCie™ extended capability structure is not utilized is made by a circuit in the target device.

20. The system of claim 18 , wherein the determination that the location corresponding to the PCie™ extended capability structure is not utilized is provided to the target device from a master device via the PCie™ bus.

Assignments (6)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER AND APPLICATION NOS. 13/237,550 AND 16/103,107 FROM THE MERGER PREVIOUSLY RECORDED ON REEL 047231 FRAME 0369. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048549/0113 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047231/0369 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2016
From: TIRUMALA, ANUP
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038366/0214 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2016
From: MOBIN, MOHAMMAD; XIA, HAITAO
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038310/0098 →
Continuity (1)
Related Publication 20170300451A1 · Oct 19, 2017