Planar memory cell architectures in resistive memory devices
To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive random access memory (ReRAM) array is provided. The ReRAM array includes a plurality of memory cells each comprising resistive memory material formed into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data bits stored by the memory cells. The ReRAM array also includes a plurality of interconnect features each comprising conductive material between adjacent memory cells formed into the layer of the substrate, and gate portions coupled onto the memory cells and configured to individually alter the resistance properties of the resistive memory material of associated memory cells responsive to at least voltages applied to the gate portions.
1. A resistive random access memory (ReRAM) array, comprising:
memory cells each comprising resistive memory material formed into a layer of a substrate and having alterable resistance properties corresponding to one or more stored data bits;
conductive interconnect features formed into the layer of the substrate between adjacent memory cells; and
gate portions coupled onto corresponding ones of the memory cells and configured to individually alter the resistance properties of the resistive memory material responsive to at least voltages applied to the gate portions.
2. The ReRAM array of claim 1 , wherein at least one of a Schottky barrier and a rectifying junction is formed between each of the gate portions and associated memory cells.
3. The ReRAM array of claim 1 , wherein the memory cells are formed by introducing the resistive memory material into the layer of the substrate, and wherein the conductive interconnect features are each formed by introducing conductive material into the layer of the substrate to conductively connect the adjacent memory cells.
4. The ReRAM array of claim 1 , wherein the gate portions comprise an n-type semiconductor material and the resistive memory material comprises a p-type metal oxide material.
5. The ReRAM array of claim 1 , wherein the gate portions comprise a p-type semiconductor material and the resistive memory material comprises an n-type metal oxide material.
6. The ReRAM array of claim 1 , wherein the resistive memory material comprises a flux linkage controlled resistor material.
7. The ReRAM array of claim 1 , comprising:
a semiconductor sublayer on which the substrate is layered, the semiconductor sublayer comprising logic circuitry configured to control at least the ReRAM array.
8. The ReRAM array of claim 1 , comprising:
the memory cells forming a data line of a data array, with ends of the data line communicatively coupled to control circuitry configured to read a series resistance property of the data line comprising the memory cells.
9. The ReRAM array of claim 1 , comprising:
the memory cells forming a data line of a data array, with the gate portions of the data line individually selectable by control circuitry to measure an associated resistance property of at least a subset of the memory cells in series with selected gate portions through an end of the data line.
10. A solid state data storage array, comprising:
one or more wordlines each comprising resistive random access memory (ReRAM) elements connected in series by metallized interconnect;
each of the ReRAM elements comprising an active channel between a source and drain, the active channel comprising resistive memory material introduced into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data stored by the associated ReRAM element;
the metallized interconnect of each of the wordlines comprising metallizing material introduced into the layer of the substrate between adjacent ReRAM elements to establish a conductive link between the adjacent ReRAM elements; and
each of the ReRAM elements comprising a gate portion positioned proximate to the active channel and configured to alter the resistance properties of the active channel responsive to at least voltages applied to the gate portion.
11. The solid state data storage array of claim 10 , comprising:
the active channels formed by at least one of diffusing, annealing, and ion implanting the resistive memory material into the layer of the substrate, and the metallized interconnect features each formed by at least one of diffusing, annealing, and ion implanting the metallizing material into the layer of the substrate to conductively connect adjacent ReRAM elements.
12. The solid state data storage array of claim 10 , comprising:
a semiconductor sublayer on which the substrate is layered, the semiconductor sublayer comprising logic circuitry configured to control at least the solid state data storage array.
13. The solid state data storage array of claim 10 , comprising:
the gate portions of the wordlines individually selectable by control circuitry to measure associated resistance properties of at least a subset of the ReRAM elements in series with selected gate portions through an end of an associated wordline.
14. The solid state data storage array of claim 13 , comprising:
ends of the wordlines each communicatively coupled to the control circuitry configured to measure at least series resistance properties across ReRAM elements comprising each of the wordlines.