NONVOLATILE SCHOTTKY BARRIER MEMORY TRANSISTOR
An apparatus for high density memory with integrated logic. Specifically, a three terminal resistive random access memory (ReRAM) device having Schottky barriers that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes an insulating layer, a source region disposed on the insulating layer, a drain region disposed on the insulating layer, a binary or complex oxide memory material, a gate dielectric layer, and a gate electrode. As voltage is applied the Schottky barrier breaks down leading to the formation of a conductive anodic filament (CAF). The CAF is non-volatile and short-circuits the reverse-biased barrier thus keeping the device in a low resistance state. Removing the CAF switches the device back to a high resistance state. Thus, a new type of semiconductor device advantageously combines computation and memory further providing for very high density NAND chains.
1 . A Schottky transistor memory device, comprising:
an insulating layer;
a source region disposed on the insulating layer;
a drain region disposed on the insulating layer;
an oxide memory material disposed on the insulating layer in between the source region and the drain region;
a gate dielectric layer disposed on the oxide memory material; and
a gate electrode disposed on the gate dielectric layer.
2 . The device of claim 1 , further comprising a first Schottky barrier disposed between the source region and the oxide memory material.
3 . The device of claim 2 , further comprising a second Schottky barrier disposed between the drain region and the oxide memory material.
4 . The device of claim 1 , wherein the source region comprises PtSi or NiSi.
5 . The device of claim 4 , wherein the drain region comprises NiSi.
6 . The device of claim 5 , wherein the oxide memory material comprises a material selected from the group consisting of the oxides of hafnium, titanium, tantalum zirconium, praseodymium calcium manganate (PCMO).
7 . The device of claim 6 , wherein the gate electrode comprises polycrystalline silicon.
8 . The device of claim 1 , wherein the gate dielectric layer is partially disposed on the source region, and partially disposed on the gate region.
9 . A Schottky transistor memory device, comprising:
an insulating layer;
a source region disposed on the insulating layer, wherein the source region has a first composition;
a drain region disposed on the insulating layer, wherein the drain region has a second composition;
a memory material disposed on the insulating layer in between the source region and the drain region, wherein the memory material has a third composition different from the first composition;
a gate dielectric layer disposed on the memory material;
a gate electrode disposed on the gate dielectric layer; and
a conductive anodic filament extending from the drain region to the memory material.
10 . The device of claim 9 , wherein the first composition of the source region comprises PtSi or NiSi.
11 . The device of claim 10 , wherein the second composition of the drain region comprises PtSi or NiSi.
12 . The device of claim 11 , wherein the third composition of the memory material comprises an oxide.
13 . The device of claim 12 , wherein the third composition of the memory material is selected from the group consisting of hafnium oxide, titanium oxide, zirconium oxide, tantalum oxide, praseodymium calcium manganate (PCMO), or mixtures thereof.
14 . The device of claim 12 , wherein the memory material, one or both of the drain and source regions are chosen from binary or complex oxides such that a Schottky barrier is formed at one or more interfaces.
15 . The device of claim 9 , wherein the second composition of the drain region comprises PtSi or NiSi.
16 . The device of claim 9 , wherein the third composition of the memory material is selected from the group consisting of hafnium oxide, titanium oxide, tantalum oxide, praseodymium calcium manganate (PCMO), or mixtures thereof.
17 . The device of claim 9 , wherein the gate dielectric layer is partially disposed on the source region and partially disposed on the gate region.
18 . A memory array comprising one or more Schottky transistor memory devices, at least one of the devices comprising:
an insulating layer;
a source region disposed on the insulating layer, wherein the source region has a first composition;
a drain region disposed on the insulating layer, wherein the drain region has a second composition;
a memory material disposed on the insulating layer in between the source region and the drain region, wherein the memory material has a third composition different from the first composition;
a gate dielectric layer disposed on the memory material;
a gate electrode disposed on the gate dielectric layer; and
a conductive anodic filament extending from the drain region to the memory material.
19 . The memory array of claim 18 , wherein the first composition of the source region comprises PtSi or NiSi.
20 . The memory array of claim 19 , wherein the second composition of the drain region comprises PtSi or NiSi.
21 . The memory array of claim 20 , wherein the third composition of the memory material is selected from the group consisting of hafnium oxide, titanium oxide, tantalum oxide, praseodymium calcium manganate (PCMO), or mixtures thereof.
22 . The memory array of claim 18 , wherein the third composition of the memory material is selected from the group consisting of hafnium oxide, titanium oxide, tantalum oxide, or mixtures thereof.