SIDEWALL INSULATED RESISTIVE MEMORY DEVICES
To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device includes an active region having resistance properties that can be modified to store one or more data bits in the resistive memory device, and at least one sidewall portion of the active region comprising a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion. The resistive memory device includes terminals configured to couple the active region to associated electrical contacts.
1 . A resistive memory device, comprising:
an active region having resistance properties that can be modified to store one or more data bits in the resistive memory device;
at least one sidewall portion of the active region comprising a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion; and
terminals configured to couple the active region to associated electrical contacts.
2 . The resistive memory device of claim 1 , comprising:
the at least one sidewall portion of the active region further configured to constrain current flow to a central portion of the active region.
3 . The resistive memory device of claim 1 , wherein the dopant increases dielectric properties of the sidewall portion of the active region, and the dopant comprises a dielectric material diffused into the sidewall portion of the active region.
4 . The resistive memory device of claim 1 , further comprising:
a gate portion proximate to the active region and configured to modify the resistance properties of the active region responsive to voltages applied to the gate portion.
5 . The resistive memory device of claim 1 , wherein the active region comprises an oxide of tantalum, and wherein the dopant comprises at least one of an oxide of hafnium and an oxide of zirconium.
6 . The resistive memory device of claim 1 , wherein a first of the terminals comprises a source terminal proximate to a first sidewall of the active region, wherein a second of the terminals comprises a drain terminal proximate to a second sidewall of the active region different than the first sidewall, wherein the at least one sidewall portion of the active region comprising the dopant comprises at least a third sidewall of the active region different than the first and second sidewalls.
7 . The resistive memory device of claim 1 , wherein the active region comprises resistive memory material deposited into a via feature created in a layer of material comprising the dopant, and wherein at least a portion of the dopant is diffused into the resistive memory material at the at least one sidewall portion of the active region.
8 . The resistive memory device of claim 1 , wherein the active region comprises a layer of resistive memory material having material comprising the dopant deposited in a via feature established in the layer of resistive memory material, and wherein at least a portion of the dopant is diffused into the resistive memory material at the at least one sidewall portion of the active region.
9 . The resistive memory device of claim 1 , wherein the active region comprises a layer of resistive memory material having the dopant deposited along a sidewall of a via feature established in the layer of resistive memory material, the dopant redeposited during creation of the via feature into a sublayer comprising the dopant.
10 . A method of manufacturing a resistive memory device, the method comprising:
forming an active region comprising a resistive memory material having resistance properties that can be electrically modified to store one or more data bits;
forming at least one sidewall portion in the active region by at least introducing a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion;
forming terminals against associated sides of the active region different than the at least one sidewall portion.
11 . The method of claim 10 , wherein the dopant increases dielectric properties of the at least one sidewall portion.
12 . The method of claim 10 , wherein the dopant comprises a dielectric material diffused into the at least one sidewall portion of the active region.
13 . The method of claim 10 , wherein the active region comprises an oxide of tantalum, and wherein the dopant comprises at least one of an oxide of hafnium and an oxide of zirconium.
14 . The method of claim 10 , wherein a first of the terminals comprises a source terminal proximate to a first sidewall of the active region, wherein a second of the terminals comprises a drain terminal proximate to a second sidewall of the active region different than the first sidewall, wherein the at least one sidewall portion of the active region comprising the dopant comprises at least a third sidewall of the active region different than the first and second sidewalls.
15 . The method of claim 10 , wherein forming the active region comprises depositing resistive memory material deposited into a via feature created in a layer of material comprising the dopant, and wherein at least a portion of the dopant is diffused into the resistive memory material at the at least one sidewall portion of the active region.
16 . The method of claim 10 , wherein forming the active region comprises first depositing a layer comprising the resistive memory material, establishing a via feature in the layer comprising the resistive memory material, depositing the dopant onto a wall of the via feature, and diffusing at least a portion of the dopant from the wall of the via feature into the resistive memory material at the at least one sidewall portion of the active region.
17 . The method of claim 10 , wherein forming the active region comprises first depositing a layer comprising the resistive memory material, establishing a via feature in the layer comprising the resistive memory material, redepositing the dopant onto a wall of the via feature from creation of the via feature into a sublayer comprising the dopant, and diffusing at least a portion of the dopant from the wall of the via feature into the resistive memory material at the at least one sidewall portion of the active region.
18 . A solid state data storage array, comprising:
one or more wordlines each comprising resistive random access memory (ReRAM) elements connected in series by interconnect, the interconnect of each of the wordlines comprising material introduced between adjacent ReRAM elements to establish a conductive link between the adjacent ReRAM elements;
each of the ReRAM elements comprising an active channel between a source and drain, the active channel comprising resistive memory material with resistance properties of the resistive memory material corresponding to data stored by the associated ReRAM element;
each of the active channels of the ReRAM elements comprising at least one sidewall portion comprising a dopant configured to suppress conductance paths in the associated active channel proximate to the at least one sidewall portion;
each of the ReRAM elements comprising a gate portion positioned proximate to the active channel and configured to alter the resistance properties of the active channel responsive to at least voltages applied to the gate portion.
19 . The solid state data storage array of claim 18 , wherein the active channel of each of the ReRAM elements comprises an oxide of tantalum, and wherein the dopant comprises at least one of an oxide of hafnium and an oxide of zirconium
20 . The solid state data storage array of claim 18 , comprising:
a semiconductor sublayer on which the ReRAM elements are layered, the semiconductor sublayer comprising logic circuitry configured to control at least the solid state data storage array.