MULTI-LAYER RESISTIVE MEMORY DEVICES
To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a multi-layer resistive random access memory (ReRAM) array is provided. Active layers of the array each comprise a plurality of ReRAM elements that each include a gate portion having a gate terminal and a memory cell portion with a source terminal and drain terminal. Insulating layers of the array alternate with the active layers and each comprise an insulating material between adjacent active layers. Wordlines span through more than one layer of the array, with each of the wordlines comprising a column of memory cell portions coupled via source terminals and drain terminals of column-associated ReRAM elements. Bitlines each span through an associated active layer of the array, with each of the bitlines comprising a row of gate portions coupled via at least gate terminals of row-associated ReRAM elements.
1 . A multi-layer resistive random access memory (ReRAM) array, comprising:
active layers of the multi-layer ReRAM array each comprising a plurality of ReRAM elements that each include a gate portion having a gate terminal and a memory cell portion with a source terminal and drain terminal;
insulating layers of the multi-layer ReRAM array that alternate with the active layers and each comprising an insulating material between adjacent active layers;
a plurality of wordlines spanning through more than one layer of the multi-layer ReRAM array, with each of the wordlines comprising a column of memory cell portions coupled via at least source terminals and drain terminals of column-associated ReRAM elements;
a plurality of bitlines each spanning in an associated active layer of the multi-layer ReRAM array, with each of the bitlines comprising a row of gate portions coupled via at least gate terminals of row-associated ReRAM elements.
2 . The ReRAM array of claim 1 , comprising:
the plurality of wordlines spanning vertically through the more than one layer of the multi-layer ReRAM array, with the vertical direction perpendicular to a surface of a wafer of semiconductor material on which the ReRAM array is formed; and
the plurality of bitlines each spanning horizontally in the associated active layer of the multi-layer ReRAM array, with the horizontal direction parallel to the surface of the wafer.
3 . The ReRAM array of claim 1 , comprising:
the memory cell portions of each of the ReRAM elements comprising resistive memory material, with resistance properties of the resistive memory material corresponding to data bits stored by the ReRAM elements.
4 . The ReRAM array of claim 3 , wherein the resistive memory material comprises a flux linkage controlled resistor material.
5 . The ReRAM array of claim 1 , comprising:
the gate portion of each of the ReRAM elements comprising a wrap-around gate element which envelops the memory cell portion on the associated active layer, with the gate portion of each of the ReRAM elements configured to selectively alter resistance properties of resistive memory material comprising associated memory cell portions.
6 . The ReRAM array of claim 5 , comprising:
individual ones of the gate portions configured to selectively alter the resistance properties of the associated memory cell portions responsive to at least a voltage applied across a corresponding bitline and wordline.
7 . The ReRAM array of claim 1 , comprising:
resistive memory material comprising the wordlines that form the columns through the more than one layer of the multi-layer ReRAM array, the resistive memory material penetrating through at least one of the active layers of the multi-layer ReRAM and at least one of the insulating layers of the multi-layer ReRAM array.
8 . The ReRAM array of claim 1 , comprising:
a semiconductor sublayer on which the multi-layer ReRAM array is layered, the semiconductor sublayer comprising logic circuitry configured to control at least the ReRAM array.
9 . The ReRAM array of claim 1 , comprising:
the ReRAM elements each comprising non-volatile memory junction field effect transistors, wherein resistances of channel paths of the non-volatile memory junction field effect transistors are altered by at least voltages applied to associated gate portions.
10 . The ReRAM array of claim 1 , comprising:
control circuitry communicatively coupled to ends of the wordlines and configured to measure at least a series resistance property of each of the wordlines; and
the control circuitry communicatively coupled to ends of the bitlines and configured to individually select ones of the bitlines to measure an associated resistance property of a subset of the ReRAM elements as a series resistance property through a bitline-selected gate portion and a selected wordline;
the control circuitry configured to determine data stored by a first of the ReRAM elements by at least processing the series resistance property of a first wordline that contains the at least one of the ReRAM elements and a resistance property of a first subset of the ReRAM elements.
11 . A resistive memory storage array, comprising:
a plurality of metallization planes interleaved with a plurality of insulating planes that form a vertically layered stackup of planar material;
a plurality of active channels comprising resistive memory material and disposed vertically through the layered stackup of planar material to establish vertical wordlines of the resistive memory storage array, with each of the active channels enveloped by gate material that isolates the active channels from at least the metallization planes; and
individual resistive memory cells defined by the gate material and proximate portions of the active channels on layers comprising the metallization planes, with the gate material of the resistive memory cells communicatively coupled by associated metallization planes to establish a plurality of horizontal bitlines.
12 . The resistive memory storage array of claim 11 , comprising:
each of the resistive memory cells configured to alter resistance properties of the resistive memory material in an associated active channel responsive to at least a voltage applied to associated gate material, with the resistance properties corresponding to at least one data bit.
13 . The resistive memory storage array of claim 11 , comprising:
the layered stackup of planar material further layered onto a semiconductor sublayer, the semiconductor sublayer comprising logic circuitry configured to control at least the resistive memory storage array.
14 . The resistive memory storage array of claim 11 , wherein the resistive memory material comprises a flux linkage controlled resistor material.
15 . The resistive memory storage array of claim 11 , comprising:
control circuitry communicatively coupled to ends of the wordlines and configured to measure at least a series resistance property of each of the wordlines; and
the control circuitry communicatively coupled to ends of the bitlines and configured to individually select ones of the bitlines to measure an associated resistance property of a subset of the resistive memory cells as a series resistance property through a bitline-selected gate portion and a selected wordline;
the control circuitry configured to determine data stored by a first of the resistive memory cells by at least processing the series resistance property of a first wordline that contains the at least one of the resistive memory cells and a resistance property of a first subset of the resistive memory cells.
16 . A method of manufacturing a multi-layer resistive random access memory (ReRAM) array, the method comprising:
forming a plurality of metallization planes interleaved with a plurality of insulating planes to establish a vertically layered stackup of planar material;
forming a plurality of active channels comprising resistive memory material disposed vertically through the layered stackup of planar material to establish vertical wordlines of the resistive memory storage array, with each of the active channels enveloped by gate material that isolates the active channels from at least the metallization planes; and
wherein individual resistive memory cells are defined by the gate material and proximate portions of the active channels on layers comprising the metallization planes, with the gate material of the resistive memory cells communicatively coupled by associated metallization planes to establish a plurality of horizontal bitlines.
17 . The method of claim 16 , further comprising:
forming the layered stackup of planar material onto at least one of a semiconductor sublayer and a metallization layer associated with the underlying semiconductor sublayer.
18 . The method of claim 17 , further comprising:
forming interconnect that communicatively couples the wordlines and bitlines to control logic of the semiconductor sublayer.
19 . The method of claim 16 , wherein the resistive memory material comprises a flux linkage controlled resistor material.
20 . The method of claim 16 , wherein the gate material comprises an n-type polycrystalline silicon material.