NON-VOLATILE SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR
The present disclosure generally relates to an apparatus for high density memory with integrated logic. A three terminal ReRAM device, which includes a p-n junction and a Schottky barrier, that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes a source region, a drain region, a first p-type or n-type oxide layer disposed between the source and drain regions, a second p-type or n-type oxide layer, and a gate electrode. As voltage is applied to the gate electrode, the Schottky barrier breaks down, leading to the formation of a filament. The filament is non-volatile and short-circuits the reverse-biased barrier, keeping the device in a low resistance state. Removing the filament by reversing the polarity of the voltage switches the device back to a high resistance state, allowing for the memory state to be readout through the gate electrode.
1 . A Schottky transistor memory device, comprising:
an insulating layer;
a source region disposed on the insulating layer;
a drain region disposed on the insulating layer;
a first oxide material layer disposed on the insulating layer in contact with the source region and the drain region;
a second layer disposed on the first oxide material layer; and
a gate electrode disposed on the second layer, wherein the first oxide material layer and the second layer form one of a p-n junction and a n-p junction.
2 . The device of claim 1 , wherein the second layer is selected from the group consisting of a second p-type or n-type material layer.
3 . The device of claim 1 , wherein the first oxide material layer is a p-type oxide material layer, and the second layer is an n-type oxide material layer.
4 . The device of claim 1 , wherein the first oxide material layer is an n-type oxide material layer, and the second layer is a p-type oxide material layer.
5 . The device of claim 1 , wherein the first oxide material-layer and the second layer comprise hafnium, titanium, or tantalum.
6 . The device of claim 1 , wherein the drain region comprises platinum, ruthenium, or nickel.
7 . The device of claim 1 , wherein an interface between the first oxide material layer and the drain region forms a Schottky barrier.
8 . The device of claim 1 , wherein an interface between the first oxide material layer and the source region forms a Schottky barrier.
9 . (canceled)
10 . A Schottky transistor memory device, comprising:
an insulating layer;
a source region disposed on the insulating layer;
a drain region disposed on the insulating layer;
a first p-type or n-type oxide material layer disposed on the insulating layer in between the source region and the drain region;
a second layer disposed on the first p-type or n-type oxide material layer;
a gate electrode disposed on the second layer; and
a conductive anodic filament extending from the drain region to the first p-type or n-type oxide material layer.
11 . The device of claim 10 , wherein the second layer is selected from the group consisting of a dielectric layer and a second p-type or n-type material layer.
12 . The device of claim 10 , wherein the first p-type or n-type oxide material layer is a p-type oxide material layer, and the second layer is an n-type oxide material layer.
13 . The device of claim 10 , wherein the first p-type or n-type oxide material layer is an n-type oxide material layer, and the second layer is a p-type oxide material layer.
14 . The device of claim 10 , wherein the first p-type or n-type oxide material layer and the second layer comprise hafnium, titanium, or tantalum.
15 . The device of claim 10 , wherein the drain region comprises platinum, ruthenium, or nickel.
16 . The device of claim 10 , wherein an interface between the first p-type or n-type oxide material layer and the drain region forms a Schottky barrier.
17 . The device of claim 10 , wherein an interface between the first p-type or n-type oxide material layer and the source region forms a Schottky barrier.
18 . The device of claim 10 , wherein the second layer is a dielectric layer and the dielectric layer is disposed on and in contact with the first p-type or n-type oxide material layer, source region and drain region.
19 . A memory array comprising one or more Schottky transistor memory devices, at least one of the devices comprising:
an insulating layer;
a source region disposed on the insulating layer;
a drain region disposed on the insulating layer;
a first p-type or n-type oxide material layer disposed on the insulating layer in between the source region and the drain region;
a second layer disposed on the first p-type or n-type oxide material layer;
a gate electrode disposed on the second layer; and
a conductive anodic filament extending from the drain region to the first p-type or n-type oxide material layer.
20 . The memory array of claim 19 , wherein the second layer is selected from the group consisting of a dielectric layer and a second p-type or n-type material layer.
21 . The memory array of claim 19 , wherein the first p-type or n-type oxide material layer is a p-type oxide material layer, and the second layer is an n-type oxide material layer.
22 . The memory array of claim 19 , wherein the first p-type or n-type oxide material layer is an n-type oxide material layer, and the second layer is a p-type oxide material layer.
23 . The memory array of claim 19 , wherein the first p-type or n-type oxide material layer and the second layer comprise hafnium, titanium, or tantalum.
24 . The memory array of claim 19 , wherein the drain region comprises platinum, ruthenium, or nickel.
25 . The memory array of claim 19 , wherein an interface between the first p-type or n-type oxide material layer and the drain region forms a Schottky barrier.
26 . The memory array of claim 19 , wherein an interface between the first p-type or n-type oxide material layer and the source region forms a Schottky barrier.
27 . The memory array of claim 19 , wherein the second layer is a dielectric layer and the dielectric layer is disposed on and in contact with the first p-type or n-type oxide material layer, source region and drain region.