Dithering a clock used to update a display to mitigate display artifacts
A display device can use clock dithering to spread the frequency spectrum of the clock signal (and the signals derived therefrom) to mitigate interference with other components or systems in a host device. However, dithering the clock signal can introduce display artifacts into the display device. For example, lines or rows in the display may flicker, the brightness of display lines may be non-uniform, or color shifts in displayed pixels. To reduce display artifacts, the embodiments herein synchronize clock dithering to a display update event. That is, the display device varies a parameter of clock dithering so that the dithering is synchronized to the display update event. In another embodiment, the clock dithering is set according to the rate at which display lines or sub-pixels are updated. In another embodiment, clock dithering is synchronized to a display frame update period.
1. A processing system for a display device, the processing system comprising:
a clock generator configured to generate a clock signal using clock dithering for updating a display of the display device during a plurality of display events, wherein the processing system is configured to vary a parameter of the clock dithering performed on the clock signal in response to the plurality of display events,
wherein a frequency of the clock signal is gradually changed between a high value and a low value during each of the plurality of display events.
2. The processing system of claim 1 , wherein the display events are display line updates, and wherein varying the parameter comprises resetting the frequency of the clock signal to a pre-determined value at a beginning of the display line updates.
3. The processing system of claim 2 , wherein varying the parameter of the clock dithering comprises:
setting the frequency of the clock signal to an integer multiple of a display frequency used when performing the display line updates in the display device.
4. The processing system of claim 1 , wherein the display events are sub-pixel update periods, wherein varying the parameter of the clock dithering comprises:
setting the frequency of the clock signal to an integer multiple of a display frequency used when updating sub-pixel colors during the sub-pixel update periods.
5. The processing system of claim 1 , wherein the display events are frame update periods, wherein varying the parameter of the clock dithering comprises:
resetting the frequency of the clock signal to a predetermined frequency during a beginning of the frame update periods.
6. The processing system of claim 5 , wherein the frequency of the clock signal is reset to the predetermined frequency at the beginning of a plurality of sequential frame update periods.
7. The processing system of claim 5 , wherein the frequency of the clock signal is reset to different predetermined frequencies at the beginning of two sequential frame update periods.
8. The processing system of claim 1 , wherein an average frequency of the clock signal during each of the plurality of display events is the same.
9. An input device, comprising:
a display comprising a plurality of display lines; and
a processing system coupled to the display, the processing system comprising a clock generator configured to generate a clock signal using clock dithering for updating the display during a plurality of display events, wherein the processing system is configured to vary a parameter of the clock dithering performed on the clock signal in response to the plurality of display events,
wherein a frequency of the clock signal is gradually changed between a high value and a low value during each of the plurality of display events.
10. The input device of claim 9 , wherein the display events are display line updates, and wherein varying the parameter comprises resetting the frequency of the clock signal to a pre-determined value at a beginning of the display line updates.
11. The input device of claim 10 , wherein varying the parameter of the clock dithering comprises:
setting the frequency of the clock signal to an integer multiple of a display frequency used when performing the display line updates.
12. The input device of claim 9 , wherein the display events are sub-pixel update periods, wherein varying the parameter of the clock dithering comprises:
setting the frequency of the clock signal to an integer multiple of a display frequency used when updating sub-pixel colors during the sub-pixel update periods.
13. The input device of claim 9 , wherein the display events are frame update periods, wherein varying the parameter of the clock dithering comprises:
resetting the frequency of the clock signal to a predetermined frequency during a beginning of the frame update periods, wherein the frequency of the clock signal is reset to the predetermined frequency at the beginning of a plurality of sequential frame update periods.
14. The input device of claim 9 , wherein varying the parameter of the clock dithering comprises:
resetting the frequency of the clock signal to a first predetermined frequency during a beginning of a first frame update period; and
resetting the frequency of the clock signal to a second predetermined frequency during a beginning of a second frame update period, wherein the first predetermined frequency is different from the second predetermined frequency and the second frame update period sequentially follows the first frame update period.
15. A method of operating a display device, the method comprising:
generating a dithered clock signal used for updating a display in the display device during a plurality of display events; and
varying a parameter of the dithered clock signal in response to the plurality of display events, wherein a frequency of the dithered clock signal is gradually changed between a high value and a low value during each of the plurality of display events.
16. The method of claim 15 , wherein the display events are display line updates and varying the parameter further comprises:
resetting the frequency of the dithered clock signal to a pre-determined value at a beginning of the display line updates.
17. The method of claim 16 , wherein varying the parameter of the clock dithering signal comprises:
setting the frequency of the dithered clock signal to an integer multiple of a display frequency used when performing the display line updates in the display device.
18. The method of claim 15 , wherein the display events are sub-pixel update periods, wherein varying the parameter of the clock dithering signal comprises:
setting the frequency of the dithered clock signal to an integer multiple of a display frequency used when updating sub-pixel colors during the sub-pixel update periods.
19. The method of claim 15 , wherein the display events are frame update periods, wherein varying the parameter of the clock dithering signal comprises:
resetting the frequency of the dithered clock signal to a predetermined frequency during a beginning of the frame update periods, wherein the frequency of the dithered clock signal is reset to the predetermined frequency at the beginning of a plurality of sequential frame update periods.
20. The method of claim 15 , wherein varying the parameter of the clock dithering signal comprises:
resetting the frequency of the dithered clock signal to a first predetermined frequency during a beginning of a first frame update period; and
resetting the frequency of the dithered clock signal to a second predetermined frequency during a beginning of a second frame update period, wherein the first predetermined frequency is different from the second predetermined frequency and the second frame update period sequentially follows the first frame update period.