Camera system encoder/decoder architecture
An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.
1. A camera system, comprising:
an image sensor chip configured to produce image data representative of light incident upon the image sensor chip;
an encoder configured to:
perform a first encoding operation on image data to produce first encoded image data and store the encoded image data in memory; and
perform a second encoding operation on image data to produce second encoded image data and output the second encoded image data; and
a decoder configured to access the first encoded image data from the memory and decode the first encoded image data to produce decoded image data, wherein the encoder is further configured to perform the second encoding operation on the decoded image data to produce the second encoded image data.
2. The camera system of claim 1 , wherein the encoder comprises a wavelet encoder, and wherein the decoder comprises a wavelet decoder.
3. The camera system of claim 1 , wherein a format of the first encoded image data is not a displayable image format.
4. The camera system of claim 1 , wherein the encoder is configured to perform the first encoding operation in response to the image sensor chip capturing the image data at an above-threshold rate.
5. The camera system of claim 1 , wherein the first encoding operation requires less processing power than the second encoding operation.
6. The camera system of claim 1 , wherein the first encoding operation requires less processing time than the second encoding operation.
7. The camera system of claim 1 , wherein the memory includes a combination read/write communication bus communicatively coupled to the encoder and the decoder, wherein the encoder is configured to write to the memory via the combination read/write communication bus, and wherein the decoder is configured to read from the memory via the combination read/write communication bus.
8. A method for capturing images by a camera system, comprising:
capturing, by an image sensor chip, image data representative of light incident upon the image sensor chip;
encoding, by an encoder of the camera system, the image data using a first encoding operation to produce first encoded image data;
storing, by the encoder, the first encoded image data in a memory;
accessing, by a decoder of the camera system, the first encoded image data from the memory;
decoding, by the decoder, the first encoded image data to produce decoded image data;
encoding, by the encoder, the decoded image data using a second encoding operation to produce second encoded image data; and
outputting, by the output, the second encoded image data.
9. The method of claim 8 , wherein the encoder comprises a wavelet encoder, and wherein the decoder comprises a wavelet decoder.
10. The method of claim 8 , wherein a format of the first encoded image data is not a displayable image format.
11. The method of claim 8 , wherein the encoder is configured to encode the image data using the first encoding operation in response to the image sensor chip capturing the image data at an above-threshold rate.
12. The method of claim 8 , wherein the first encoding operation requires less processing power than the second encoding operation.
13. The method of claim 8 , wherein the first encoding operation requires less processing time than the second encoding operation.
14. The method of claim 8 , wherein the memory includes a combination read/write communication bus communicatively coupled to the encoder and the decoder, wherein the encoder is configured to write to the memory via the combination read/write communication bus, and wherein the decoder is configured to read from the memory via the combination read/write communication bus.
15. A integrated circuit chip for capturing images in a camera system, comprising:
an encoder configured to:
perform a first encoding operation on image data captured by an image sensor chip to produce first encoded image data and store the encoded image data in memory; and
perform a second encoding operation on image data to produce second encoded image data and output the second encoded image data; and
a decoder configured to access the first encoded image data from the memory and decode the first encoded image data to produce decoded image data, wherein the encoder is further configured to perform the second encoding operation on the decoded image data to produce the second encoded image data.
16. The integrated circuit chip of claim 15 , wherein the encoder comprises a wavelet encoder, and wherein the decoder comprises a wavelet decoder.
17. The integrated circuit chip of claim 15 , wherein a format of the first encoded image data is not a displayable image format.
18. The integrated circuit chip of claim 15 , wherein the encoder is configured to perform the first encoding operation on the image data in response to the image sensor chip capturing the image data at an above-threshold rate.
19. The integrated circuit chip of claim 15 , wherein the first encoding operation requires less processing power or less processing time than the second encoding operation.
20. The integrated circuit chip of claim 15 , wherein the memory includes a combination read/write communication bus communicatively coupled to the encoder and the decoder, wherein the encoder is configured to write to the memory via the combination read/write communication bus, and wherein the decoder is configured to read from the memory via the combination read/write communication bus.