IP Library Granted Patent US 9,997,612
Granted Patent B2
US 9,997,612 · App. 15/487,660 · Granted Jun 12, 2018

Compound semiconductor device and method of manufacturing the same

Inventor: Junji Kotani (Atsugi, JP)
Assignee: FUJITSU LIMITED
H01L29/66462H01L21/0254H01L21/0262H01L21/02378H01L21/02381H01L21/02458H01L29/2003H01L29/7787
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Quick Facts
Patent No.
US 9,997,612
App. No.
15/487,660
Granted
Jun 12, 2018
Kind
B2
Abstract

A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon.

Claims (21)

1. A method of manufacturing a compound semiconductor device comprising:

forming an impurity-containing region containing impurities in a semiconductor substrate, the impurities being Fe, C, Au, or Mg, or combination thereof;

forming an initial layer containing AlN over the semiconductor substrate;

forming a channel layer over the initial layer;

forming a carrier supply layer over the channel layer; and

forming a gate electrode, a source electrode and a drain electrode over the carrier supply layer.

2. The method according to claim 1 , wherein the semiconductor substrate is a silicon substrate or a silicon carbide substrate.

3. The method according to claim 1 , wherein a level of the impurities is higher than an upper edge of a valence band of silicon by 0.25 eV or more.

4. The method according to claim 1 , wherein a level of the impurities is lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the level of the impurities being higher than an upper edge of a valence band of silicon.

5. The method according to claim 1 , further comprising forming a buffer layer containing AlGaN between the semiconductor substrate and the channel layer.

6. The method according to claim 5 , wherein the buffer layer is formed over an initial layer containing AlN, the initial layer formed between the semiconductor substrate and the channel layer.

7. The method according to claim 1 , further comprising forming a superlattice buffer layer in which first nitride semiconductor layers and second nitride semiconductor layers are repeatedly stacked.

8. The method according to claim 7 , wherein the superlattice buffer layer is formed over a buffer layer containing AlGaN, the buffer layer formed between the semiconductor substrate and the channel layer.

9. The method according to claim 7 , wherein the first semiconductor layer contains AlN.

10. The method according to claim 9 , wherein a thickness of the first semiconductor layer is 2 nm or less.

11. The method according to claim 7 , wherein the second semiconductor layer contains AlGaN.

12. The method according to claim 7 , wherein the first nitride semiconductor layers and the second nitride semiconductor layers are repeatedly stacked 80 periods in the superlattice buffer layer.

13. The method according to claim 1 , wherein the initial layer contains the impurities.

14. The method according to claim 1 , wherein the impurities exist at an interface between the semiconductor substrate and the initial layer.

15. The method according to claim 1 , wherein an average impurity concentration is 1 ×10 18 cm −3 or more in a region from an upper surface to a depth of 50 nm of the semiconductor substrate.

16. The method according to claim 1 , wherein a carrier life time in the semiconductor substrate is 1 ×10 −9 seconds or less.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
Priority Claims (1)
JP 2014-129563 · Jun 24, 2014 · national
Continuity (2)
Division 14747060 · Jun 23, 2015
Related Publication 20170222016A1 · Aug 3, 2017