Power fail handling using stop commands

1. A data storage device comprising:

non-volatile memory circuits; and

a controller configured to:

determine that a power fail event has occurred;

determine, in response to the determination that the power fail event has occurred, which of the non-volatile memory circuits are executing a first type of memory commands; and

issue a stop command to the determined non-volatile memory circuits to stop execution of the first type of memory commands.

2. The data storage device of claim 1 , wherein the first type of memory commands comprise erase commands.

3. The data storage device of claim 1 , wherein the first type of memory commands comprise program commands for writing a first type of data.

4. The data storage device of claim 3 , wherein the first type of data comprises non-acknowledged host data.

5. The data storage device of claim 1 , wherein the controller is further configured to:

issue, in response to the issued stop command, a second type of memory commands to the determined non-volatile memory circuits.

6. The data storage device of claim 5 , wherein the second type of memory commands comprise program commands for writing a second type of data.

7. The data storage device of claim 6 , wherein the second type of data comprises one or more of system data or acknowledged host data.

8. The data storage device of claim 1 , wherein the stop command comprises a suspend command to suspend execution of the first type of memory commands, wherein the suspended first type of memory commands are resumed in response to a subsequent command from the controller.

9. The data storage device of claim 1 , wherein the stop command comprises a terminate command to terminate execution of the first type of memory commands, wherein the terminated first type of memory commands are not resumed in response to a subsequent command from the controller.

10. The data storage device of claim 1 , wherein the controller is further configured to:

write data from a volatile memory to the non-volatile memory circuits before the power from an internal power source drops below a predetermined threshold, the non-volatile memory circuits being powered by the internal power source when the power fail event has occurred.

11. The data storage device of claim 10 , wherein the internal power source includes a battery or a capacitive element.

12. The data storage device of claim 1 , wherein the determined non-volatile memory circuits transition from a programming state to a suspend state based on the issued stop command, wherein the determined non-volatile memory circuits transition from the suspend state back to the programming state based on a subsequent program command from the controller.

13. The data storage device of claim 1 , wherein the determined non-volatile memory circuits transition from an erase state to a terminate state based on the issued stop command, wherein the determined non-volatile memory circuits transition from the terminate state back to the erase state based on a subsequent erase command from the controller.

14. The data storage device of claim 1 , wherein the controller is configured to read, in response to the determination that the power fail event has occurred, one or more command queues in a random access memory, and wherein the controller determines which of the non-volatile memory circuits are executing the first type of memory commands from the one or more command queues.

15. A system comprising:

a plurality of flash memory circuits;

a random access memory (RAM); and

a controller communicatively coupled to the plurality of flash memory circuits, the controller configured to:

determine that a power fail event has occurred;

determine, in response to the determination that the power fail event has occurred, which of the plurality of flash memory circuits are executing an erase command or a program command; and

stop execution of either the erase command or the program command based on a stop command being issued to the determined flash memory circuits.

16. The system of claim 15 , wherein the controller is further configured to:

issue, in response to the issued stop command, a write command to the determined flash memory circuits; and

write, in response to the issued write command, data to at least one of the plurality of flash memory circuits before power from an internal power source drops below a predetermined threshold.

17. The system of claim 15 , wherein the controller is further configured to:

initiate a subsequent program command to the determined flash memory circuits to resume the stopped program command.

18. The system of claim 15 , wherein the determined non-volatile memory circuits transition from a first state to a second state based on the issued stop command, wherein the determined non-volatile memory circuits transition from the second state back to the first state based on a subsequent command from the controller, wherein the first state includes a program state and the second state includes a suspend state, wherein the first state includes an erase state and the second state includes a terminate state.

19. A method comprising:

determining that a power fail event has occurred;

determining, in response to the determination that the power fail event has occurred, which flash memory circuits in a data storage device are executing an erase command or a program command; and

issuing a stop command to the determined flash memory circuits to terminate the erase command or to suspend the program command.

20. The method of claim 19 , further comprising:

issuing, in response to the issued stop command, a write command to the determined flash memory circuits; and

write, in response to the issued write command, data to at least one of the determined flash memory circuits before power from an internal power source drops below a predetermined threshold.

21. A system comprising:

means for determining that a power fail event has occurred in flash storage;

means for determining, in response to the determination that the power fail event has occurred, which flash memory circuits in the flash storage are executing an erase command or a program command; and

means for issuing a stop command to the determined flash memory circuits to terminate the erase command or to suspend the program command.