Video processing system using low-cost video encoding/decoding architecture
A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.
1. A video processing system comprising:
a merging circuit, arranged to receive a plurality of input video frames, and merge a plurality of video frames to create a merged video frame, wherein the video frames are derived from the input video frames, respectively; and
a video encoder, arranged to encode the merged video frame to output a bitstream;
wherein the input video frames comprise a first input video frame with a first resolution and a second input video frame with a second resolution, and the first resolution is different from the second resolution; and
wherein the video frames comprise a first video frame derived from the first input video frame and a second video frame derived from the second input video frame, an uppermost pixel row of the first video frame included in the merged video frame is a first part of an uppermost pixel row of the merged video frame, and an uppermost pixel row of the second video frame included in the merged video frame is a second part of the uppermost pixel row of the merged video frame.
2. The video processing system of claim 1 , wherein the merging circuit is further arranged to resize at least one of the first input video frame and the second input video frame to generate at least one resized video frame, and the first video frame and the second video frame comprise the at least one resized video frame.
3. A video processing system comprising:
a merging circuit, arranged to receive a plurality of input video frames, and merge a plurality of video frames to create a merged video frame, wherein the video frames are derived from the input video frames, respectively; and
a video encoder, arranged to encode the merged video frame to output a bitstream;
wherein the input video frames comprise a first input video frame with a first resolution and a second input video frame with a second resolution, and the first resolution is different from the second resolution; and
wherein the video frames comprise a first video frame derived from the first input video frame and a second video frame derived from the second input video frame, a lowermost pixel row of the first video frame included in the merged video frame is a first part of a lowermost pixel row of the merged video frame, and a lowermost pixel row of the second video frame included in the merged video frame is a second part of the lowermost pixel row of the merged video frame.
4. The video processing system of claim 3 , wherein the merging circuit is further arranged to resize at least one of the first input video frame and the second input video frame to generate at least one resized video frame, and the first video frame and the second video frame comprise the at least one resized video frame.
5. A video processing system comprising:
a merging circuit, arranged to receive a plurality of input video frames, and merge a plurality of video frames to create a merged video frame, wherein the video frames are derived from the input video frames, respectively; and
a video encoder, arranged to encode the merged video frame to output a bitstream;
wherein the input video frames comprise a first input video frame with a first resolution and a second input video frame with a second resolution, and the first resolution is different from the second resolution; and
wherein the video frames comprise a first video frame derived from the first input video frame and a second video frame derived from the second input video frame, a leftmost pixel column of the first video frame included in the merged video frame is a first part of a pixel column of the merged video frame, and a leftmost pixel column of the second video frame included in the merged video frame is a second part of the pixel column of the merged video frame.
6. The video processing system of claim 5 , wherein the merging circuit is further arranged to resize at least one of the first input video frame and the second input video frame to generate at least one resized video frame, and the first video frame and the second video frame comprise the at least one resized video frame.
7. A video processing system comprising:
a merging circuit, arranged to receive a plurality of input video frames, and merge a plurality of video frames to create a merged video frame, wherein the video frames are derived from the input video frames, respectively; and
a video encoder, arranged to encode the merged video frame to output a bitstream;
wherein the input video frames comprise a first input video frame with a first resolution and a second input video frame with a second resolution, and the first resolution is different from the second resolution; and
wherein the video frames comprise a first video frame derived from the first input video frame and a second video frame derived from the second input video frame, a rightmost pixel column of the first video frame included in the merged video frame is a first part of a pixel column of the merged video frame, and a rightmost pixel column of the second video frame included in the merged video frame is a second part of the pixel column of the merged video frame.
8. The video processing system of claim 7 , wherein the merging circuit is further arranged to resize at least one of the first input video frame and the second input video frame to generate at least one resized video frame, and the first video frame and the second video frame comprise the at least one resized video frame.
9. The video processing system of claim 1 , wherein the merging circuit receives the input video frames from different video sources, respectively.
10. The video processing system of claim 1 , wherein the input video frames have a same timestamp.
11. The video processing system of claim 1 , wherein the video encoder comprises:
a processing circuit, arranged to process pixel data of the merged video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients; and
a universal binary entropy (UBE) syntax encoder, arranged to process a plurality of syntax elements to generate UBE syntax data, wherein the encoding-related data are represented by the syntax elements, the processing circuit operates according to a video coding standard, the video coding standard supports arithmetic encoding, and the UBE syntax data contain no arithmetic-encoded syntax data.