Optically aligned hybrid semiconductor device and method
Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.
1. A method of optically aligning a hybrid semiconductor device, the method comprising:
a) providing a first semiconductor chip including a first alignment surface and a first optical waveguide, wherein the first alignment surface is positioned with a first offset from an optical axis of the first optical waveguide;
b) providing a second semiconductor chip including a second alignment surface and a second optical waveguide, wherein the second alignment surface is positioned with a second offset from an optical axis of the second optical waveguide, wherein the second offset is epitaxially-defined in the second semiconductor chip to complement the first offset, so that when the first and second alignment surfaces abut, the first and second waveguides are aligned; and
c) bringing the first and second semiconductor chips together until the first and second alignment surfaces come to a stop against each other, with the first and second alignment surfaces being in direct contact with each other and the first and second optical waveguides being optically coupled;
wherein step b) includes:
i) growing a stack of epitaxial layers including a waveguiding layer sandwiched between first and second cladding layers, and
ii) forming the second alignment surface by selectively etching the stack of epitaxial layers using a layer-selective etch to expose an area of an epitaxy-defined layer surface of one of the epitaxial layers of the stack;
wherein step i) includes growing a buffer layer over the second cladding layer; and
wherein step ii) includes selectively etching at least one recess in the buffer layer to form at least one first pillar with flat outer ends forming the second alignment surface.
2. The method according to claim 1 , wherein step i) includes growing an etch-stop layer between the buffer layer and the second cladding layer, and
wherein step ii) includes selectively etching the stack of the epitaxial layers up to the etch stop layer to expose at least an area thereof to form each of the recesses and first pillars.
3. The method according to claim 1 , wherein the first semiconductor chip includes second pillars with flat end faces defining the first alignment surface; and
wherein step c) includes abutting the end faces of the first and second pillars.
4. A method of optically aligning a hybrid semiconductor device, the method comprising:
a) providing a first semiconductor chip including a first alignment surface and a first optical waveguide, wherein the first alignment surface is positioned with a first offset from an optical axis of the first optical waveguide;
b) providing a second semiconductor chip including a second alignment surface and a second optical waveguide, wherein the second alignment surface is positioned with a second offset from an optical axis of the second optical waveguide, wherein the second offset is epitaxially-defined in the second semiconductor chip to complement the first offset, so that when the first and second alignment surfaces abut, the first and second waveguides are aligned; and
c) bringing the first and second semiconductor chips together until the first and second alignment surfaces come to a stop against each other, with the first and second alignment surfaces being in direct contact with each other and the first and second optical waveguides being optically coupled;
wherein step b) includes:
iii) growing a stack of epitaxial layers including a waveguiding layer sandwiched between first and second cladding layers, and
iv) forming the second alignment surface by selectively etching the stack of epitaxial layers using a layer-selective etch to expose an area of an epitaxy-defined layer surface of one of the epitaxial layers of the stack;
wherein the second alignment surface comprises at least an area of an epitaxially-defined layer surface of the waveguiding layer;
wherein step ii) includes selectively etching the stack of the epitaxial layers up to the waveguiding layer to expose at least an area thereof to form the second alignment surface.
5. The method according to claim 4 , wherein step ii) includes selectively etching recesses in the second cladding layer up to the waveguiding layer; and
wherein the first semiconductor chip includes pillars, including flat end faces defining the first alignment surface; and
wherein step c) includes disposing the pillars in the recesses until the first alignment surface abuts the second alignment surface.
6. The method according to claim 1 , wherein step ii) includes etching the second cladding layer and the waveguiding layer to define a ridge waveguide in the waveguiding layer, and to enable electrical contact to the first cladding layer; and
providing a first electrode in contact with the first cladding layer for electrically biasing the first cladding layer in an area of the ridge waveguide; and
providing a second electrode in contact with the second cladding layer for electrically biasing the second cladding layer in an area of the ridge waveguide.
7. The method according to claim 1 , wherein step ii) includes etching the second cladding layer and the waveguiding layer to enable electrical contact with the first and second cladding layers; and
providing a first electrode extending into contact with the first cladding layer for electrically biasing the first cladding layer; and
providing a second electrode extending though the first cladding layer and the waveguiding layer into contact with the second cladding layer for electrically biasing the second cladding layer.
8. An optically aligned hybrid semiconductor device, comprising:
a first semiconductor chip including a first alignment surface and a first optical waveguide, wherein the first alignment surface is positioned with a first offset from an optical axis of the first optical waveguide;
a second semiconductor chip including a second alignment surface and a second optical waveguide, wherein the second alignment surface is positioned with a second offset from an optical axis of the second optical waveguide, wherein the second offset is epitaxially-defined in the second semiconductor chip to complement the first offset, so that when the first and second alignment surfaces abut, the first and second waveguides are aligned; and
wherein the first and second alignment surfaces abut each other, with the first and second alignment surfaces being in direct contact with each other and the first and second optical waveguides being optically coupled; and
wherein the second semiconductor chip includes a stack of epitaxial layers including a waveguiding layer sandwiched between first and second cladding layers, wherein the second alignment surface comprises an exposed area of an epitaxy-defined layer surface of one of the epitaxial layers of the stack;
wherein the stack includes a buffer layer over the second cladding layer; and
wherein at least one recess in the buffer layer defines at least one first pillar with flat outer ends forming the second alignment surface.
9. The device according to claim 8 , wherein the stack includes an etch-stop layer between the buffer layer and the second cladding layer, and
wherein the recesses extend up to the etch stop layer to expose at least an area thereof to form each of the first pillars.
10. The device according to claim 8 , wherein the first semiconductor chip includes second pillars with flat end faces defining the first alignment surface; and
wherein the end faces of the first pillars abut the end faces of the second pillars.
11. An optically aligned hybrid semiconductor device, comprising:
a first semiconductor chip including a first alignment surface and a first optical waveguide, wherein the first alignment surface is positioned with a first offset from an optical axis of the first optical waveguide;
a second semiconductor chip including a second alignment surface and a second optical waveguide, wherein the second alignment surface is positioned with a second offset from an optical axis of the second optical waveguide, wherein the second offset is epitaxially-defined in the second semiconductor chip to complement the first offset, so that when the first and second alignment surfaces abut, the first and second waveguides are aligned; and
wherein the first and second alignment surfaces abut each other, with the first and second alignment surfaces being in direct contact with each other and the first and second optical waveguides being optically coupled; and
wherein the second semiconductor chip includes a stack of epitaxial layers including a waveguiding layer sandwiched between first and second cladding layers, wherein the second alignment surface comprises an exposed area of an epitaxy-defined layer surface of one of the epitaxial layers of the stack;
wherein the second alignment surface comprises at least an area of an epitaxially-defined layer surface of the waveguiding layer.
12. The device according to claim 11 , wherein the first semiconductor chip includes pillars, including flat end faces defining the first alignment surface.
13. The device according to claim 8 , wherein the second cladding layer and the waveguiding layer include trenches defining a ridge waveguide in the waveguiding layer; and
wherein the device further comprises:
a first electrode in contact with the first cladding layer for electrically biasing the first cladding layer in an area of the ridge waveguide; and
a second electrode in contact with the second cladding layer for electrically biasing the second cladding layer in an area of the ridge waveguide.
14. The device according to claim 8 , further comprising:
a first electrode extending into contact with the first cladding layer for electrically biasing the first cladding layer; and
a second electrode extending though the first cladding layer and the waveguiding layer into contact with the second cladding layer for electrically biasing the second cladding layer.
15. The method according to claim 4 , wherein step ii) includes etching the second cladding layer and the waveguiding layer to define a ridge waveguide in the waveguiding layer, and to enable electrical contact to the first cladding layer; and
providing a first electrode in contact with the first cladding layer for electrically biasing the first cladding layer in an area of the ridge waveguide; and
providing a second electrode in contact with the second cladding layer for electrically biasing the second cladding layer in an area of the ridge waveguide.
16. The method according to claim 4 , wherein step ii) includes etching the second cladding layer and the waveguiding layer to enable electrical contact with the first and second cladding layers; and
providing a first electrode extending into contact with the first cladding layer for electrically biasing the first cladding layer in an area of the ridge waveguide; and
providing a second electrode extending though the first cladding layer and the waveguiding layer into contact with the second cladding layer for electrically biasing the second cladding layer.
17. The device according to claim 11 , wherein the second cladding layer and the waveguiding layer include trenches defining a ridge waveguide in the waveguiding layer; and
wherein the device further comprises:
a first electrode in contact with the first cladding layer for electrically biasing the first cladding layer in an area of the ridge waveguide; and
a second electrode in contact with the second cladding layer for electrically biasing the second cladding layer in an area of the ridge waveguide.
18. The device according to claim 11 , further comprising:
a first electrode extending into contact with the first cladding layer for electrically biasing the first cladding layer in an area of the ridge waveguide; and
a second electrode extending though the first cladding layer and the waveguiding layer into contact with the second cladding layer for electrically biasing the second cladding layer.