IP Library Granted Patent US 10,044,529
Granted Patent B2
US 10,044,529 · App. 15/795,374 · Granted Aug 7, 2018

Time-domain equalizer and signal processing method thereof

Inventors: Yu-Shen Chou (Hsinchu Hsien, TW); Fong-Shih Wei (Hsinchu Hsien, TW); Ko-Yin Lai (Hsinchu Hsien, TW)
Assignee: MSTAR SEMICONDUCTOR, INC.
H04L25/03019H04L2025/03636
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Quick Facts
Patent No.
US 10,044,529
App. No.
15/795,374
Granted
Aug 7, 2018
Kind
B2
Abstract

A time-domain equalizer includes a delay circuit, a weighting circuit, a controller and a summation circuit. The delay circuit receives an equalized signal and accordingly generates M delayed signals for an equalized signal. The weighting circuit applies an m th weighting of M weightings to an m th delayed signal of the M delayed signals to generate an m th weighted signal. The summation circuit sums up the M weighted signals, according to which the equalized signal is updated. The controller iteratively updates the M weightings according to a vector {right arrow over (e)} n,p =[e n,p,1 . . . e n,p,M ], where the symbol e n,p,j is defined as e n,p,j =Σ k (z[k]*z[k−D p,j ]*), the symbol n is an iteration index, k is a sample index, z[k] is a k th sample of the equalized signal, j is an integer index between 1 and M, and D p,j represents a time delay amount corresponding to a j th delayed signal of the M delayed signals.

Claims (374)

1. A time-domain equalizer, comprising:

a delay circuit, receiving an equalized signal, and accordingly generating M delayed signals, where M is a positive integer greater than 1;

a weighting circuit, adopting M weightings, and applying an m th weighting of the M weightings on an m th delayed signal of the M delay signals to generate an m th weighted signal, where m is an integer index between 1 and M, wherein M weighted signals are generated accordingly;

a controller, iteratively updating the M weightings according to a vector {right arrow over (e)} n,p =[e n,p,1 . . . e n,p,M ], where e n,p,j is defined as e n,p,j =Σ k (z[k]*z[k−D p,j ]*), n represents an iteration index, k represents a sample index, z[k] is a k th sample of the equalized signal, p corresponds to a p th echo signal, j is an integer index between 1 and M, D p,j represents a j th time delay amount corresponding to a j th delayed signal of the M delayed signals, and z[k−D p,j ]* represents z[k] delayed by delay D p,j ; and

summation circuit, summing up the M weighted signals, according to which the equalized signal is updated.

2. The time-domain equalizer according to claim 1 , wherein the controller updates the M weightings adopted by the weighting circuit according to an equation:

w

n

+

1

,

p

=

[

w

n

+

1

,

p

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1

w

n

+

1

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]

=

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+

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,

where μ represents an adjustable parameter in a least mean square (LMS) algorithm; and

the vector {right arrow over (z)} n,p,m is:

[Σ k z[k−D p,m ]*z[k−D p,1 ]* . . . Σ k z[k−D p,m ]*z[k−D p,M ]*],

where D p,m represents an m th delay amount.

3. The time-domain equalizer according to claim 1 , wherein:

the controller further comprises an adaptive adjusting circuit that determines M parameters [k n,p,1 . . . k n,p,M ] according to the M weightings [w n,p,1 . . . w n,p,M ]; and

the controller updates the M weightings according to an equation:

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where μ is an adjustable parameter in a least mean square (LMS) algorithm, and the vector {right arrow over (z)} n,p,m is:

[Σ k z[k−D p,m ]*z[k−D p,1 ]* . . . Σ k z[k−D p,m ]*z[k−D p,M ]*],

where D p,m represents an m th delay amount.

4. A signal processing method, comprising:

receiving an equalized signal, and accordingly generating M delayed signals, where M is a positive integer;

adopting M weightings, and applying an m th weighting of the M weightings to an m th delayed signal of the M delay signals to generate an m th weighted signal, where m is an integer index between 1 and M;

iteratively updating the M weightings according to a vector {right arrow over (e)} n,p =[e n,p,1 . . . e n,p,M ]. where e n,p,j is defined as e n,p,j =Σ k (z[k]*z[k−D p,j ]*), n represents an iteration index, k represents a sample index, z[k] is a k th sample of the equalized signal, p corresponds to a p th echo signal, j is an integer index between 1 and M, D p,j represents a j th time delay amount corresponding to a j th delayed signal of the M delayed signals, and z[k−D p,j ]* represents z[k] delayed by delay D p,j ; and

summing up the M weighted signals to update the equalized signal.

5. The signal processing method according to claim 4 , wherein the step of iteratively updating the M weightings comprising updating the M weightings according to an equation:

w

_

n

+

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,

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=

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z

n

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n

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M

T

]

where μ represents an adjustable parameter in a least mean square (LMS) algorithm; and

the vector {right arrow over (z)} n,p,m is:

[Σ k z[k−D p,m ]*z[k−D p,1 ]* . . . Σ k z[k−D p,m ]*z[k−D p,M ]*],

where D p,m represents an m th delay amount.

6. The signal processing method according to claim 4 , further comprising:

determining the M parameters [k n,p,1 . . . k n,p,M ] according to the M weightings [w n,p,1 . . . w n,p,M ];

and the step of iteratively updating the M weightings comprises updating the M weightings according to an equation:

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+

1

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=

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+

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[

k

n

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p

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n

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p

z

n

,

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,

1

T

k

n

,

p

,

M

e

n

,

p

z

n

,

p

,

M

T

]

where μ is an adjustable parameter in a least mean square (LMS) algorithm, and the vector {right arrow over (z)} n,p,m is:

[Σ k z[k−D p,m ]*z[k−D p,1 ]* . . . Σ k z[k−D p,m ]*z[k−D p,M ]*],

where D p,m represents an m th delay amount.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2021
From: MEDIATEK INC.
To: XUESHAN TECHNOLOGIES INC.
Reel/Frame 056593/0167 →
MERGER Recorded Jun 12, 2020
From: MSTAR SEMICONDUCTOR, INC.
To: MEDIATEK INC.
Reel/Frame 052931/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2017
From: CHOU, YU-SHEN; WEI, FONG-SHIH; LAI, KO-YIN
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 043969/0359 →
Priority Claims (1)
TW 105142447 A · Dec 21, 2016 · national
Continuity (1)
Related Publication 20180176046A1 · Jun 21, 2018